Wide-input dynamic range 1 MHz clock ultra-low supply flip-flop

• Main Authors: Siek, Liter, Palaniappan, Arjun Ramaswami
• Other Authors: School of Electrical and Electronic Engineering
• Format: Article
• Language: English
• Published: 2018
• Subjects: DRNTU::Engineering::Electrical and electronic engineering; Wide-input Dynamic Range; Ultra-low Supply Voltage
• Online Access: https://hdl.handle.net/10356/89420; http://hdl.handle.net/10220/46252
• Institution: Nanyang Technological University

A new wide-input dynamic range flip-flop capable of operation at an ultra-low supply voltage of 0.16 V is presented. The proposed flip-flop named as capacitively boosted sense-amplifier flip-flop (CB-SAFF) utilises a capacitively boosted sense-amplifier master stage to sense the data signals and amplify them to a voltage higher than the supply and below the ground for driving the slave latch stage with improved strength. Using the same size of input/output transistors and load capacitance, the proposed CB-SAFF outperforms existing state-of-the-art sense-amplifier flip-flop designs at a low supply voltage operation from 0.16 to 0.6 V in terms of power delay product and clock to output propagation delay performance metrics. In addition, the proposed CB-SAFF can also sample low-swing data signals down to 0.2 V even at a 0.16 V supply voltage and 1 MHz clock frequency, thus making it highly suitable for applications that demand high speed and low power consumption such as for use in ultra-low voltage Internet of Things, wireless sensor nodes and smart motes.