Wide-input dynamic range 1 MHz clock ultra-low supply flip-flop

• Main Authors: Siek, Liter, Palaniappan, Arjun Ramaswami
• 其他作者: School of Electrical and Electronic Engineering
• 格式: Article
• 語言: English
• 出版: 2018
• 主題: DRNTU::Engineering::Electrical and electronic engineering; Wide-input Dynamic Range; Ultra-low Supply Voltage
• 在線閱讀: https://hdl.handle.net/10356/89420; http://hdl.handle.net/10220/46252

A new wide-input dynamic range flip-flop capable of operation at an ultra-low supply voltage of 0.16 V is presented. The proposed flip-flop named as capacitively boosted sense-amplifier flip-flop (CB-SAFF) utilises a capacitively boosted sense-amplifier master stage to sense the data signals and amp...