A micropower low-voltage multiplier with reduced spurious switching

• Main Authors: Gwee, Bah Hwee, Chang, Joseph Sylvester, Chong, Kwen-Siong
• Other Authors: School of Electrical and Electronic Engineering
• Format: Article
• Language: English
• Published: 2009
• Subjects: DRNTU::Engineering::Electrical and electronic engineering
• Online Access: https://hdl.handle.net/10356/90378; http://hdl.handle.net/10220/4643
• Institution: Nanyang Technological University

We describe a micropower 16 16-bit multiplier (18.8 W/MHz @1.1 V) for low-voltage power-critical low speed ( 5 MHz) applications including hearing aids. We achieve the micropower operation by substantially reducing (by 62% and 79% compared to conventional 16 16-bit and 32 32-bit designs respectively) the spurious switching in the Adder Block in the multiplier. The approach taken is to use latches to synchronize the inputs to the adders in the Adder Block in a predetermined chronological sequence. The hardware penalty of the latches is small because the latches are integrated (as opposed to external latches) into the adder, termed the Latch Adder (LA). By means of the LAs and timing, the number of switchings (spurious and that for computation) is reduced from 5 6 and 10 per adder in the Adder Block in conventional 16 16-bit and 32 32-bit designs respectively to 2 in our designs. Based on simulations and measurements on prototype ICs (0.35 m three metal dual poly CMOS process), we show that our 16 16-bit design dissipates 32% less power, is 20% slower but has 20% better energy-delay-product (EDP) than conventional 16 16-bit multipliers. Our 32 32-bit design is estimated to dissipate 53% less power, 29% slower but is 39% better EDP than the conventional general multiplier.