Robust on-chip signaling by staggered and twisted bundle

Robust on-chip signaling by staggered and twisted bundle

Existing shield insertion for multiple signal nets can lead to a nonuniformly distributed, capacitive-coupling length and inductive return paths, introducing large delays and delay variation by crosstalk. This article discusses a twisted,...

Full description

Saved in:
Bibliographic Details
Main Authors: Yu, Hao, He, Lei, Chang, Frank Mau Chung
Other Authors: School of Electrical and Electronic Engineering
Format: Article
Language:English
Published: 2010
Subjects:
DRNTU::Engineering::Electrical and electronic engineering
Online Access:https://hdl.handle.net/10356/90518
http://hdl.handle.net/10220/6237
Tags: Add Tag
No Tags, Be the first to tag this record!
Institution: Nanyang Technological University
Language: English
Description
Summary:Existing shield insertion for multiple signal nets can lead to a nonuniformly distributed, capacitive-coupling length and inductive return paths, introducing large delays and delay variation by crosstalk. This article discusses a twisted, staggered interconnect structure that reduces both inductive and capacitive crosstalk. The proposed design reduces delay by 25% and reduces delay variation by 25 compared to designs employing coplanar shields.

Similar Items