Robust on-chip signaling by staggered and twisted bundle
Existing shield insertion for multiple signal nets can lead to a nonuniformly distributed, capacitive-coupling length and inductive return paths, introducing large delays and delay variation by crosstalk. This article discusses a twisted,...
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sg-ntu-dr.10356-905182020-03-07T13:57:30Z Robust on-chip signaling by staggered and twisted bundle Yu, Hao He, Lei Chang, Frank Mau Chung School of Electrical and Electronic Engineering DRNTU::Engineering::Electrical and electronic engineering Existing shield insertion for multiple signal nets can lead to a nonuniformly distributed, capacitive-coupling length and inductive return paths, introducing large delays and delay variation by crosstalk. This article discusses a twisted, staggered interconnect structure that reduces both inductive and capacitive crosstalk. The proposed design reduces delay by 25% and reduces delay variation by 25 compared to designs employing coplanar shields. Published version 2010-04-20T03:38:35Z 2019-12-06T17:49:06Z 2010-04-20T03:38:35Z 2019-12-06T17:49:06Z 2009 2009 Journal Article Yu, H., He, L., & Chang, M. C. (2009). Robust on-chip signaling by staggered and twisted bundle. IEEE Design and Test of Computers. 26(5), 92-104. 0740-7475 https://hdl.handle.net/10356/90518 http://hdl.handle.net/10220/6237 10.1109/MDT.2009.121 148331 en IEEE design and test of computers © 2009 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE. This material is presented to ensure timely dissemination of scholarly and technical work. Copyright and all rights therein are retained by authors or by other copyright holders. All persons copying this information are expected to adhere to the terms and constraints invoked by each author's copyright. In most cases, these works may not be reposted without the explicit permission of the copyright holder. http://www.ieee.org/portal/site This material is presented to ensure timely dissemination of scholarly and technical work. Copyright and all rights therein are retained by authors or by other copyright holders. All persons copying this information are expected to adhere to the terms and constraints invoked by each author's copyright. In most cases, these works may not be reposted without the explicit permission of the copyright holder. 13 p. application/pdf |
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DRNTU::Engineering::Electrical and electronic engineering Yu, Hao He, Lei Chang, Frank Mau Chung Robust on-chip signaling by staggered and twisted bundle |
description |
Existing shield insertion for multiple signal nets can lead to a nonuniformly distributed,
capacitive-coupling length and inductive return paths, introducing
large delays and delay variation by crosstalk. This article discusses a twisted,
staggered interconnect structure that reduces both inductive and capacitive
crosstalk. The proposed design reduces delay by 25% and reduces delay variation
by 25 compared to designs employing coplanar shields. |
author2 |
School of Electrical and Electronic Engineering |
author_facet |
School of Electrical and Electronic Engineering Yu, Hao He, Lei Chang, Frank Mau Chung |
format |
Article |
author |
Yu, Hao He, Lei Chang, Frank Mau Chung |
author_sort |
Yu, Hao |
title |
Robust on-chip signaling by staggered and twisted bundle |
title_short |
Robust on-chip signaling by staggered and twisted bundle |
title_full |
Robust on-chip signaling by staggered and twisted bundle |
title_fullStr |
Robust on-chip signaling by staggered and twisted bundle |
title_full_unstemmed |
Robust on-chip signaling by staggered and twisted bundle |
title_sort |
robust on-chip signaling by staggered and twisted bundle |
publishDate |
2010 |
url |
https://hdl.handle.net/10356/90518 http://hdl.handle.net/10220/6237 |
_version_ |
1681045732036968448 |