System-level design of a delta-sigma modulator target for next generation wireless application
Delta-sigma (Δ∑) converters have been widely used in wireless communications as they provide the most economic speed-accuracy tradeoff. This paper presents the system-level design of a multi-bit continuous-time (CT) Δ∑ analog-to-digital converter (ADC) targeting for the next generation wireless appl...
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| Main Authors: | , , |
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| Other Authors: | |
| Format: | Conference or Workshop Item |
| Language: | English |
| Published: |
2010
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| Subjects: | |
| Online Access: | https://hdl.handle.net/10356/90664 http://hdl.handle.net/10220/6288 |
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| Institution: | Nanyang Technological University |
| Language: | English |
| Summary: | Delta-sigma (Δ∑) converters have been widely used in wireless communications as they provide the most economic speed-accuracy tradeoff. This paper presents the system-level design of a multi-bit continuous-time (CT) Δ∑ analog-to-digital converter (ADC) targeting for the next generation wireless application. The modulator topology is determined based on the application requirements using MATLAB software. The nonidealities associated with the multi-bit CT Δ∑ modulator, such as excess loop delay, system clock jitter, integrator nonideality and multi-bit digital-toanalog converter (DAC) element mismatch, are also modeled in the system-level. With all the nonidealities included, the designed modulator achieves a dynamic range (DR) of 74dB (12 bits) in a 50-MHz signal bandwidth. |
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