System-level design of a delta-sigma modulator target for next generation wireless application

• Main Authors: Qiu, Xiaobo, Siek, Liter, Tiew, Kei Tee
• Other Authors: School of Electrical and Electronic Engineering
• Format: Conference or Workshop Item
• Language: English
• Published: 2010
• Subjects: DRNTU::Engineering::Electrical and electronic engineering
• Online Access: https://hdl.handle.net/10356/90664; http://hdl.handle.net/10220/6288
• Institution: Nanyang Technological University

Delta-sigma (Δ∑) converters have been widely used in wireless communications as they provide the most economic speed-accuracy tradeoff. This paper presents the system-level design of a multi-bit continuous-time (CT) Δ∑ analog-to-digital converter (ADC) targeting for the next generation wireless application. The modulator topology is determined based on the application requirements using MATLAB software. The nonidealities associated with the multi-bit CT Δ∑ modulator, such as excess loop delay, system clock jitter, integrator nonideality and multi-bit digital-toanalog converter (DAC) element mismatch, are also modeled in the system-level. With all the nonidealities included, the designed modulator achieves a dynamic range (DR) of 74dB (12 bits) in a 50-MHz signal bandwidth.