Power-efficient explicit-pulsed dual-edge triggered sense-amplifier flip-flops

• Main Authors: Phyu, Myint Wai, Fu, Kang Kang, Goh, Wang Ling, Yeo, Kiat Seng
• Other Authors: School of Electrical and Electronic Engineering
• Format: Article
• Language: English
• Published: 2010
• Subjects: DRNTU::Engineering::Electrical and electronic engineering::Electronic circuits
• Online Access: https://hdl.handle.net/10356/90676; http://hdl.handle.net/10220/6319
• Institution: Nanyang Technological University

A novel explicit-pulsed dual-edge triggered sense-amplifier flip-flop (DET-SAFF) for low-power and high-performance applications is presented in this paper. By incorporating the dual-edge triggering mechanism in the new fast latch and employing conditional precharging, the DET-SAFF is able to achieve low-power consumption that has small delay. To further reduce the power consumption at low switching activities, a clock-gated sense-amplifier (CG-SAFF) is engaged. Extensive post-layout simulations proved that the proposed DET-SAFF exhibits both the low-power and high-speed properties, with delay and power reduction of up to 43.3% and 33.5% of those of the prior art, respectively. When the switching activity is less than 0.5, the proposed CG-SAFF demonstrates its superiority in terms of power reduction. During zero input switching activity, CG-SAFF can realize up to 86% in power saving. Lastly, a modification to the proposed circuit has led to an improved common-mode rejection ratio (CMRR) DET-SAFF.