Bit-error-rate performance of intra-chip wireless interconnect systems

Bit-error-rate performance of intra-chip wireless interconnect systems

This Letter evaluates the bit-error rate (BER) performance of a coherent binary phase-shift keying interconnect system operating on an intra-chip wireless channel at 15 GHz. Results show that the system perf...

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Bibliographic Details
Main Author:	Zhang, Yue Ping
Other Authors:	School of Electrical and Electronic Engineering
Format:	Article
Language:	English
Published:	2010
Subjects:	DRNTU::Engineering::Electrical and electronic engineering::Electronic systems
Online Access:	https://hdl.handle.net/10356/91332 http://hdl.handle.net/10220/6324
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Institution:	Nanyang Technological University
Language:	English

Description
Summary:	This Letter evaluates the bit-error rate (BER) performance of a coherent binary phase-shift keying interconnect system operating on an intra-chip wireless channel at 15 GHz. Results show that the system performance degrades with the separation distance and the data rate. A high data rate at 2 Gb/s with a low BER 10 5 over the entire chip of size 20 20 mm can be achieved with the transmitted power of 10 dBm.