Bit-error-rate performance of intra-chip wireless interconnect systems
This Letter evaluates the bit-error rate (BER) performance of a coherent binary phase-shift keying interconnect system operating on an intra-chip wireless channel at 15 GHz. Results show that the system perf...
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sg-ntu-dr.10356-913322020-03-07T14:02:39Z Bit-error-rate performance of intra-chip wireless interconnect systems Zhang, Yue Ping School of Electrical and Electronic Engineering DRNTU::Engineering::Electrical and electronic engineering::Electronic systems This Letter evaluates the bit-error rate (BER) performance of a coherent binary phase-shift keying interconnect system operating on an intra-chip wireless channel at 15 GHz. Results show that the system performance degrades with the separation distance and the data rate. A high data rate at 2 Gb/s with a low BER 10 5 over the entire chip of size 20 20 mm can be achieved with the transmitted power of 10 dBm. Published version 2010-08-20T00:51:26Z 2019-12-06T18:03:48Z 2010-08-20T00:51:26Z 2019-12-06T18:03:48Z 2004 2004 Journal Article Zhang, Y. P. (2004). Bit-error-rate performance of intra-chip wireless interconnect systems. IEEE Communications Letters. 8(1), 39-41. 1089-7798 https://hdl.handle.net/10356/91332 http://hdl.handle.net/10220/6324 10.1109/LCOMM.2003.822514 en IEEE communications letters © 2004 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE. This material is presented to ensure timely dissemination of scholarly and technical work. Copyright and all rights therein are retained by authors or by other copyright holders. All persons copying this information are expected to adhere to the terms and constraints invoked by each author's copyright. In most cases, these works may not be reposted without the explicit permission of the copyright holder. http://www.ieee.org/portal/site This material is presented to ensure timely dissemination of scholarly and technical work. Copyright and all rights therein are retained by authors or by other copyright holders. All persons copying this information are expected to adhere to the terms and constraints invoked by each author's copyright. In most cases, these works may not be reposted without the explicit permission of the copyright holder. 3 p. application/pdf |
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DRNTU::Engineering::Electrical and electronic engineering::Electronic systems Zhang, Yue Ping Bit-error-rate performance of intra-chip wireless interconnect systems |
description |
This Letter evaluates the bit-error rate (BER) performance
of a coherent binary phase-shift keying interconnect system
operating on an intra-chip wireless channel at 15 GHz. Results
show that the system performance degrades with the separation
distance and the data rate. A high data rate at 2 Gb/s with a low
BER 10 5 over the entire chip of size 20 20 mm can be
achieved with the transmitted power of 10 dBm. |
author2 |
School of Electrical and Electronic Engineering |
author_facet |
School of Electrical and Electronic Engineering Zhang, Yue Ping |
format |
Article |
author |
Zhang, Yue Ping |
author_sort |
Zhang, Yue Ping |
title |
Bit-error-rate performance of intra-chip wireless interconnect systems |
title_short |
Bit-error-rate performance of intra-chip wireless interconnect systems |
title_full |
Bit-error-rate performance of intra-chip wireless interconnect systems |
title_fullStr |
Bit-error-rate performance of intra-chip wireless interconnect systems |
title_full_unstemmed |
Bit-error-rate performance of intra-chip wireless interconnect systems |
title_sort |
bit-error-rate performance of intra-chip wireless interconnect systems |
publishDate |
2010 |
url |
https://hdl.handle.net/10356/91332 http://hdl.handle.net/10220/6324 |
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1681040354611036160 |