RFCMOS unit width optimization technique

• Main Authors: Tong, Ah Fatt, Lim, Wei Meng, Sia, Choon Beng, Yeo, Kiat Seng, Teng, Zee Long, Ng, Pei Fern
• Other Authors: School of Electrical and Electronic Engineering
• Format: Article
• Language: English
• Published: 2009
• Subjects: DRNTU::Engineering::Electrical and electronic engineering
• Online Access: https://hdl.handle.net/10356/91416; http://hdl.handle.net/10220/4657
• Institution: Nanyang Technological University

In this paper, we demonstrate a unit width (Wf) optimization technique based on their unity short-circuit current gain frequency (ft), unilateral power gain frequency (f MAX), and high-frequency (HF) noise for RFCMOS transistors. Our results show that the trend for the above figures-of-merit (FOMs) with respect to the Wf change is different; hence, some tradeoff is required to obtain the optimum Wf value. During the HF noise analysis, a newFOMis proposed to study the Wf effect on the HF noise performance. In our experiment, the flicker noise of the transistor is also measured and the result shows that the change in Wf does not affect the noise spectral density at the low-frequency range. This technique enables RF engineers to optimize the transistor’s layout and helps to select the optimum Wf for transistors used in specific circuit design such as the low-noise amplifier, voltage-controlled oscillator, and mixer. Furthermore, by using layout optimized transistors in the RF circuit, the optimal circuit’s performance can be easily achieved and, thus, greatly reduced the circuit development time. In the aspect of RF device modeling, by knowing the optimum Wf for a particular process or technology, the number of transistors to model is reduced and, hence, greatly shortens the RF modeling development time for existing and future technologies.