A low-power 16×16-b parallel multiplier utilizing pass-transistor logic
This paper describes a low-power 16x16-b parallel very large scale integration multiplier, designed and fabricated using a 0.8- m double-metal double-poly BiCMOS process. In order to achieve low-power operation, the multiplier was designed utilizing mainly pass-transistor (PT) logic circuits. The in...
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| Main Authors: | , , |
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| Format: | Article |
| Language: | English |
| Published: |
2009
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| Subjects: | |
| Online Access: | https://hdl.handle.net/10356/91516 http://hdl.handle.net/10220/6009 |
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| Institution: | Nanyang Technological University |
| Language: | English |
| Summary: | This paper describes a low-power 16x16-b parallel very large scale integration multiplier, designed and fabricated using a 0.8- m double-metal double-poly BiCMOS process. In order to achieve low-power operation, the multiplier was designed utilizing mainly pass-transistor (PT) logic circuits. The inherent nonfull-swing nature of PT logic circuits were taken full advantage of, without significantly compromising the speed performance of the overall circuit implementation. New circuit implementations for the partial-product generator and the partial-product addition circuitry have been proposed, simulated, and fabricated. Experimental results showed that the worst case multiplication time of the test chip is 10.4 ns at a supply voltage of 3.3 V, and the average power dissipation is 38 mW at a frequency of 10 MHz. |
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