A low-voltage micropower asynchronous multiplier with shift-add multiplication approach

• Main Authors: Gwee, Bah Hwee, Chang, Joseph Sylvester, Shi, Yiqiong, Chua, Chien Chung, Chong, Kwen-Siong
• Other Authors: School of Electrical and Electronic Engineering
• Format: Article
• Language: English
• Published: 2010
• Subjects: DRNTU::Engineering::Electrical and electronic engineering
• Online Access: https://hdl.handle.net/10356/91586; http://hdl.handle.net/10220/6227
• Institution: Nanyang Technological University

The design of a low-voltage micropower asynchronous (async) signed truncated multiplier based on a shift–add structure for power-critical applications such as the low-clock-rate ( 4 MHz) hearing aids is described. The emphases of the design are micropower operation and small IC area, and these attributes are achieved in several ways. First, a maximum of three signed power-of-two terms accompanied with sign magnitude data representation is used for the multiplier operand. Second, the least significant partial products are truncated to yield a 16-bit signed product. An error correction methodology is proposed to mitigate, where appropriate, the arising truncation errors. The errors arising from truncation and the effectiveness of the error correction are analytically derived. Third, a low-power shifter design and an internal latch adder are adopted. Finally, a power-efficient speculative delay line is proposed to time the async operation of the various circuit modules. A comparison with competing synchronous and async designs shows that the proposed design features the lowest power dissipation (5.86 W at 1.1 V and 1 MHz) and a very competitive IC area (0.08 mm² using a 0.35-µm CMOS process). The application of the proposed multiplier for realizing a digital filter for a hearing aid is given.