An area efficient high turn ratio monolithic transformer for silicon RFIC

A novel way of manufacturing an on-chip...

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Main Authors:	Lim, Chee Chong, Yeo, Kiat Seng, Chew, Kok Wai Johnny, Lim, Suh Fei, Boon, Chirn Chye, Qiu, Ping, Do, Manh Anh, Chan, Lap
Other Authors:	School of Electrical and Electronic Engineering
Format:	Conference or Workshop Item
Language:	English
Published:	2010
Subjects:	DRNTU::Engineering::Electrical and electronic engineering::Integrated circuits
Online Access:	https://hdl.handle.net/10356/91616 http://hdl.handle.net/10220/6381
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Institution:	Nanyang Technological University
Language:	English

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spelling	sg-ntu-dr.10356-916162020-03-07T13:24:46Z An area efficient high turn ratio monolithic transformer for silicon RFIC Lim, Chee Chong Yeo, Kiat Seng Chew, Kok Wai Johnny Lim, Suh Fei Boon, Chirn Chye Qiu, Ping Do, Manh Anh Chan, Lap School of Electrical and Electronic Engineering IEEE Radio Frequency Integrated Circuits Symposium (2008 : Atlanta, Georgia, US) Chartered Semiconductor Manufacturing Ltd DRNTU::Engineering::Electrical and electronic engineering::Integrated circuits A novel way of manufacturing an on-chip transformer that produces high inductance ratio (LSec/LPri > 30) with excellent area efficiency is presented. This technique uses an electrical all-round coupling effect of a conductor A (Primary Coil), having large effective width, and a densely routed conductor B (Secondary Coil). Thus, a high turn ratio monolithic transformer, using minimum die size, is realizable on silicon. The coil having the dense routing can also be doubled up as a monolithic RF choke on silicon. In this work, area efficiency is compared between various type of existing transformer structures (i.e. Interleaved and Stacked transformer), based on unit inductance. The method presented is fully compatible to all the foundry standard CMOS processes. Published version 2010-08-31T06:07:39Z 2019-12-06T18:08:59Z 2010-08-31T06:07:39Z 2019-12-06T18:08:59Z 2008 2008 Conference Paper Lim, C. C., Yeo K. S., Chew, K. W., Lim, S. F., Boon, C. C., Qiu, P., et al. (2008). An area efficient high turn ratio monolithic transformer for silicon RFIC. IEEE Radio Frequency Integrated Circuits Symposium: Atlanta,GA,USA, (pp.167-170). https://hdl.handle.net/10356/91616 http://hdl.handle.net/10220/6381 10.1109/RFIC.2008.4561410 en © 2008 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE. This material is presented to ensure timely dissemination of scholarly and technical work. Copyright and all rights therein are retained by authors or by other copyright holders. All persons copying this information are expected to adhere to the terms and constraints invoked by each author's copyright. In most cases, these works may not be reposted without the explicit permission of the copyright holder. http://www.ieee.org/portal/site This material is presented to ensure timely dissemination of scholarly and technical work. Copyright and all rights therein are retained by authors or by other copyright holders. All persons copying this information are expected to adhere to the terms and constraints invoked by each author's copyright. In most cases, these works may not be reposted without the explicit permission of the copyright holder. 4 p. application/pdf
institution	Nanyang Technological University
building	NTU Library
country	Singapore
collection	DR-NTU
language	English
topic	DRNTU::Engineering::Electrical and electronic engineering::Integrated circuits
spellingShingle	DRNTU::Engineering::Electrical and electronic engineering::Integrated circuits Lim, Chee Chong Yeo, Kiat Seng Chew, Kok Wai Johnny Lim, Suh Fei Boon, Chirn Chye Qiu, Ping Do, Manh Anh Chan, Lap An area efficient high turn ratio monolithic transformer for silicon RFIC
author2	School of Electrical and Electronic Engineering
author_facet	School of Electrical and Electronic Engineering Lim, Chee Chong Yeo, Kiat Seng Chew, Kok Wai Johnny Lim, Suh Fei Boon, Chirn Chye Qiu, Ping Do, Manh Anh Chan, Lap
format	Conference or Workshop Item
author	Lim, Chee Chong Yeo, Kiat Seng Chew, Kok Wai Johnny Lim, Suh Fei Boon, Chirn Chye Qiu, Ping Do, Manh Anh Chan, Lap
author_sort	Lim, Chee Chong
title	An area efficient high turn ratio monolithic transformer for silicon RFIC
title_short	An area efficient high turn ratio monolithic transformer for silicon RFIC
title_full	An area efficient high turn ratio monolithic transformer for silicon RFIC
title_fullStr	An area efficient high turn ratio monolithic transformer for silicon RFIC
title_full_unstemmed	An area efficient high turn ratio monolithic transformer for silicon RFIC
title_sort	area efficient high turn ratio monolithic transformer for silicon rfic
publishDate	2010
url	https://hdl.handle.net/10356/91616 http://hdl.handle.net/10220/6381
_version_	1681049578091053056
description	A novel way of manufacturing an on-chip transformer that produces high inductance ratio (LSec/LPri > 30) with excellent area efficiency is presented. This technique uses an electrical all-round coupling effect of a conductor A (Primary Coil), having large effective width, and a densely routed conductor B (Secondary Coil). Thus, a high turn ratio monolithic transformer, using minimum die size, is realizable on silicon. The coil having the dense routing can also be doubled up as a monolithic RF choke on silicon. In this work, area efficiency is compared between various type of existing transformer structures (i.e. Interleaved and Stacked transformer), based on unit inductance. The method presented is fully compatible to all the foundry standard CMOS processes.

An area efficient high turn ratio monolithic transformer for silicon RFIC

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