Roundoff noise analysis of signals represented using signed power-of-two terms
It is a well-known fact that the multiplication of a number by an integer power-of-two is a very simple process in binary arithmetic. Hence, digital filters whose coefficient values are integer power-of-two are essentially multiplierless. The design of digital filters with power-of-two coefficient v...
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| Main Authors: | , |
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| 格式: | Article |
| 語言: | English |
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2009
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| 在線閱讀: | https://hdl.handle.net/10356/91619 http://hdl.handle.net/10220/5987 |
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| 機構: | Nanyang Technological University |
| 語言: | English |
| 總結: | It is a well-known fact that the multiplication of a number by an integer power-of-two is a very simple process in binary arithmetic. Hence, digital filters whose coefficient values are integer power-of-two are essentially multiplierless. The design of digital filters with power-of-two coefficient values require timeconsuming optimization process and may not always be possible in some applications such as in adaptive filtering. Since hardware circuitry for real-time conversion of a binary integer into a sum of a limited number of signed power-of-two (SPT) terms is available, if the signal is expressed in SPT terms, i.e., in digit code, the filter is also multiplierless even though the coefficient values are not SPT. When each signal data is rounded to a limited number of SPT terms, a roundoff noise representing the roundoff error is introduced. In the SPT space, the quantization step size is nonuniform and so the roundoff noise characteristic is different from that produced when the quantization step size is uniform. This paper presents an analysis for the roundoff noise of signal represented using a limited number of SPT terms. The result is useful for determining the number of SPT terms required to represent a signal subject to a given roundoff noise. |
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