IP watermarking using incremental technology mapping at logic synthesis level

IP watermarking using incremental technology mapping at logic synthesis level

This paper proposes an adaptive watermarking technique by modulating some closed cones in an originally optimized logic network (master design) for technology mapping. The headroom of each disjoint closed cone is evaluated based on its slack and slack sustainability. The notion of slack sustainabili...

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書目詳細資料
Main Authors:	Cui, Aijiao, Chang, Chip Hong, Tahar, Sofiène
其他作者:	School of Electrical and Electronic Engineering
格式:	Article
語言:	English
出版:	2010
主題:	DRNTU::Engineering::Electrical and electronic engineering
在線閱讀:	https://hdl.handle.net/10356/93106 http://hdl.handle.net/10220/6259
標簽:	添加標簽沒有標簽, 成為第一個標記此記錄!
機構:	Nanyang Technological University
語言:	English

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