Scalable and modular memory-based systolic architectures for discrete Hartley transform

• Main Authors: Meher, Pramod Kumar, Srikanthan, Thambipillai, Patra, Jagdish Chandra
• Other Authors: School of Computer Engineering
• Format: Article
• Language: English
• Published: 2011
• Subjects: DRNTU::Engineering::Computer science and engineering::Computer systems organization::Processor architectures
• Online Access: https://hdl.handle.net/10356/94247; http://hdl.handle.net/10220/7091
• Institution: Nanyang Technological University

In this paper, we present a design framework for scalable memory-based implementation of the discrete Hartley transform (DHT) using simple and efficient systolic and systolic-like structures for short and prime transform lengths, as well as, for lengths 4 and 8. We have used the proposed short-length structures to construct highly modular architectures for higher transform lengths by a new prime-factor implementation approach. The structures proposed for the prime-factor DHT, interestingly, do not involve any transposition hardware/time. Besides, it is shown here that an N-point DHT can be computed efficiently from two (N/2)-point DHTs of its even- and odd-indexed input subsequences in a recursive manner using a ROM-based multiplication stage. Apart from flexibility of implementation, the proposed structures offer significantly lower area-time complexity compared with the existing structures. The proposed schemes of computation of the DHT can conveniently be scaled not only for higher transform lengths but also according to the hardware constraint or the throughput requirement of the application.