Scalable and modular memory-based systolic architectures for discrete Hartley transform

• Main Authors: Meher, Pramod Kumar, Srikanthan, Thambipillai, Patra, Jagdish Chandra
• 其他作者: School of Computer Engineering
• 格式: Article
• 語言: English
• 出版: 2011
• 主題: DRNTU::Engineering::Computer science and engineering::Computer systems organization::Processor architectures
• 在線閱讀: https://hdl.handle.net/10356/94247; http://hdl.handle.net/10220/7091
• 機構: Nanyang Technological University

In this paper, we present a design framework for scalable memory-based implementation of the discrete Hartley transform (DHT) using simple and efficient systolic and systolic-like structures for short and prime transform lengths, as well as, for lengths 4 and 8. We have used the proposed short-lengt...