A lean FPGA soft processor built using a DSP block

As Field Programmable Gate Arrays (FPGAs) have advanced, the capabilities and variety of embedded resources have increased. In the last decade, signal processing has become one of the main driving applications for FPGA adoption, so FPGA vendors tailored their architectures to such applications. The...

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Main Authors:	Fahmy, Suhaib A., Maskell, Douglas L., Cheah, Hui Yan, Kulkarni, Chidamber
Other Authors:	School of Computer Engineering
Format:	Conference or Workshop Item
Language:	English
Published:	2013
Subjects:	DRNTU::Engineering::Computer science and engineering
Online Access:	https://hdl.handle.net/10356/97975 http://hdl.handle.net/10220/12233
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Institution:	Nanyang Technological University
Language:	English

id	sg-ntu-dr.10356-97975
record_format	dspace
spelling	sg-ntu-dr.10356-979752020-05-28T07:18:05Z A lean FPGA soft processor built using a DSP block Fahmy, Suhaib A. Maskell, Douglas L. Cheah, Hui Yan Kulkarni, Chidamber School of Computer Engineering International symposium on Field Programmable Gate Arrays (2012) DRNTU::Engineering::Computer science and engineering As Field Programmable Gate Arrays (FPGAs) have advanced, the capabilities and variety of embedded resources have increased. In the last decade, signal processing has become one of the main driving applications for FPGA adoption, so FPGA vendors tailored their architectures to such applications. The resulting embedded digital signal processing (DSP) blocks have now advanced to the point of supporting a wide range of operations. In this paper, we explore how these DSP blocks can be applied to general computation. We show that the DSP48E1 blocks in Xilinx Virtex-6 devices support a wide range of standard processor instructions which can be designed into the core of a basic processor with minimal additional logic usage. 2013-07-25T06:15:55Z 2019-12-06T19:48:57Z 2013-07-25T06:15:55Z 2019-12-06T19:48:57Z 2012 2012 Conference Paper Cheah, H. Y., Fahmy, S. A., Maskell, D. L., & Kulkarni, C. (2012). A lean FPGA soft processor built using a DSP block. Proceedings of the ACM/SIGDA international symposium on Field Programmable Gate Arrays. https://hdl.handle.net/10356/97975 http://hdl.handle.net/10220/12233 10.1145/2145694.2145734 en © 2012 ACM.
institution	Nanyang Technological University
building	NTU Library
country	Singapore
collection	DR-NTU
language	English
topic	DRNTU::Engineering::Computer science and engineering
spellingShingle	DRNTU::Engineering::Computer science and engineering Fahmy, Suhaib A. Maskell, Douglas L. Cheah, Hui Yan Kulkarni, Chidamber A lean FPGA soft processor built using a DSP block
description	As Field Programmable Gate Arrays (FPGAs) have advanced, the capabilities and variety of embedded resources have increased. In the last decade, signal processing has become one of the main driving applications for FPGA adoption, so FPGA vendors tailored their architectures to such applications. The resulting embedded digital signal processing (DSP) blocks have now advanced to the point of supporting a wide range of operations. In this paper, we explore how these DSP blocks can be applied to general computation. We show that the DSP48E1 blocks in Xilinx Virtex-6 devices support a wide range of standard processor instructions which can be designed into the core of a basic processor with minimal additional logic usage.
author2	School of Computer Engineering
author_facet	School of Computer Engineering Fahmy, Suhaib A. Maskell, Douglas L. Cheah, Hui Yan Kulkarni, Chidamber
format	Conference or Workshop Item
author	Fahmy, Suhaib A. Maskell, Douglas L. Cheah, Hui Yan Kulkarni, Chidamber
author_sort	Fahmy, Suhaib A.
title	A lean FPGA soft processor built using a DSP block
title_short	A lean FPGA soft processor built using a DSP block
title_full	A lean FPGA soft processor built using a DSP block
title_fullStr	A lean FPGA soft processor built using a DSP block
title_full_unstemmed	A lean FPGA soft processor built using a DSP block
title_sort	lean fpga soft processor built using a dsp block
publishDate	2013
url	https://hdl.handle.net/10356/97975 http://hdl.handle.net/10220/12233
_version_	1681059565539426304

A lean FPGA soft processor built using a DSP block

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