An 8mW ultra low power 60GHz direct-conversion receiver with 55dB gain and 4.9dB noise figure in 65nm CMOS
An ultra low power direct-conversion receiver is demonstrated for V-band 60GHz applications in 65nm CMOS process. The power consumption is significantly reduced by the design of low-power low noise amplifier (LNA), transconductance mixer and variable gain amplifier (VGA). A compact quadrature-hybrid...
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sg-ntu-dr.10356-990962020-03-07T13:24:49Z An 8mW ultra low power 60GHz direct-conversion receiver with 55dB gain and 4.9dB noise figure in 65nm CMOS Shang, Yang Cai, Deyun Fei, Wei Yu, Hao Ren, Junyan School of Electrical and Electronic Engineering IEEE International Symposium on Radio-Frequency Integration Technology (2012 : Singapore) DRNTU::Engineering::Electrical and electronic engineering An ultra low power direct-conversion receiver is demonstrated for V-band 60GHz applications in 65nm CMOS process. The power consumption is significantly reduced by the design of low-power low noise amplifier (LNA), transconductance mixer and variable gain amplifier (VGA). A compact quadrature-hybrid coupler is developed for transconductance mixer for the reduction of both power and area. The proposed receiver (0.34mm2 chip area) is measured with 8mW power, the minimum single-side-band (SSB) noise figure (NF) of 4.9dB, and the maximum power conversion gain of 55dB. Accepted version 2013-08-01T01:52:13Z 2019-12-06T20:03:20Z 2013-08-01T01:52:13Z 2019-12-06T20:03:20Z 2012 2012 Conference Paper Shang, Y., Cai, D., Fei, W., Yu, H., & Ren, J. (2012). An 8mW ultra low power 60GHz direct-conversion receiver with 55dB gain and 4.9dB noise figure in 65nm CMOS. 2012 IEEE International Symposium on Radio-Frequency Integration Technology (RFIT), 47-49. https://hdl.handle.net/10356/99096 http://hdl.handle.net/10220/12696 10.1109/RFIT.2012.6401609 en © 2012 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works. The published version is available at: [http://dx.doi.org/10.1109/RFIT.2012.6401609]. application/pdf |
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DRNTU::Engineering::Electrical and electronic engineering Shang, Yang Cai, Deyun Fei, Wei Yu, Hao Ren, Junyan An 8mW ultra low power 60GHz direct-conversion receiver with 55dB gain and 4.9dB noise figure in 65nm CMOS |
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An ultra low power direct-conversion receiver is demonstrated for V-band 60GHz applications in 65nm CMOS process. The power consumption is significantly reduced by the design of low-power low noise amplifier (LNA), transconductance mixer and variable gain amplifier (VGA). A compact quadrature-hybrid coupler is developed for transconductance mixer for the reduction of both power and area. The proposed receiver (0.34mm2 chip area) is measured with 8mW power, the minimum single-side-band (SSB) noise figure (NF) of 4.9dB, and the maximum power conversion gain of 55dB. |
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School of Electrical and Electronic Engineering |
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School of Electrical and Electronic Engineering Shang, Yang Cai, Deyun Fei, Wei Yu, Hao Ren, Junyan |
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Conference or Workshop Item |
author |
Shang, Yang Cai, Deyun Fei, Wei Yu, Hao Ren, Junyan |
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Shang, Yang |
title |
An 8mW ultra low power 60GHz direct-conversion receiver with 55dB gain and 4.9dB noise figure in 65nm CMOS |
title_short |
An 8mW ultra low power 60GHz direct-conversion receiver with 55dB gain and 4.9dB noise figure in 65nm CMOS |
title_full |
An 8mW ultra low power 60GHz direct-conversion receiver with 55dB gain and 4.9dB noise figure in 65nm CMOS |
title_fullStr |
An 8mW ultra low power 60GHz direct-conversion receiver with 55dB gain and 4.9dB noise figure in 65nm CMOS |
title_full_unstemmed |
An 8mW ultra low power 60GHz direct-conversion receiver with 55dB gain and 4.9dB noise figure in 65nm CMOS |
title_sort |
8mw ultra low power 60ghz direct-conversion receiver with 55db gain and 4.9db noise figure in 65nm cmos |
publishDate |
2013 |
url |
https://hdl.handle.net/10356/99096 http://hdl.handle.net/10220/12696 |
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1681047789563281408 |