An 8mW ultra low power 60GHz direct-conversion receiver with 55dB gain and 4.9dB noise figure in 65nm CMOS
An ultra low power direct-conversion receiver is demonstrated for V-band 60GHz applications in 65nm CMOS process. The power consumption is significantly reduced by the design of low-power low noise amplifier (LNA), transconductance mixer and variable gain amplifier (VGA). A compact quadrature-hybrid...
Saved in:
Main Authors: | Shang, Yang, Cai, Deyun, Fei, Wei, Yu, Hao, Ren, Junyan |
---|---|
Other Authors: | School of Electrical and Electronic Engineering |
Format: | Conference or Workshop Item |
Language: | English |
Published: |
2013
|
Subjects: | |
Online Access: | https://hdl.handle.net/10356/99096 http://hdl.handle.net/10220/12696 |
Tags: |
Add Tag
No Tags, Be the first to tag this record!
|
Institution: | Nanyang Technological University |
Language: | English |
Similar Items
-
A 16-mW 1-GS/s with 49.6-dB SNDR TI-SAR ADC for software-defined radio in 65-nm CMOS
by: Qiu, Lei, et al.
Published: (2019) -
D-band surface-wave modulator and signal source with 40 dB extinction ratio and 3.7 mW output power in 65 nm CMOS
by: Liang, Yuan, et al.
Published: (2020) -
A 4 GHz 60 dB variable gain amplifier with tunable DC offset cancellation in 65 nm CMOS
by: Kumar, Thangarasu Bharatha, et al.
Published: (2015) -
A 0.013-mm2 0.53-mW/Gb/s 32-Gb/s hybrid analog equalizer under 21-dB channel loss in 65-nm CMOS
by: Balachandran, Arya, et al.
Published: (2020) -
P1dB optimization methodology for 130 nm SiGe BiCMOS 60GHz power amplifier
by: Wu, Wenguang, et al.
Published: (2015)