SRAM-based NATURE: A dynamically reconfigurable FPGA based on 10T low-power SRAMs
We presented a hybrid CMOS/nanotechnology reconfigurable architecture (NATURE), earlier. It was based on CMOS logic and nano RAMs. It used the concept of temporal logic folding and fine-grain (e.g., cycle-level) dynamic reconfiguration to increase logic density by an order of magnitude. This dynamic...
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sg-ntu-dr.10356-998512020-05-28T07:19:14Z SRAM-based NATURE: A dynamically reconfigurable FPGA based on 10T low-power SRAMs Jha, Niraj K. Lin, Ting-Jung Zhang, Wei School of Computer Engineering DRNTU::Engineering::Computer science and engineering::Hardware::Logic design We presented a hybrid CMOS/nanotechnology reconfigurable architecture (NATURE), earlier. It was based on CMOS logic and nano RAMs. It used the concept of temporal logic folding and fine-grain (e.g., cycle-level) dynamic reconfiguration to increase logic density by an order of magnitude. This dynamic reconfiguration is done intra-circuit rather than inter-circuit. However, the previous design of NATURE required fine-grained distribution of nano RAMs throughout the field-programmable gate array (FPGA) architecture. Since the fabrication process of nano RAMs is not mature yet, this prevents immediate exploitation of NATURE. In this paper, we present a NATURE architecture that is based on CMOS logic and CMOS SRAMs that are used for on-chip dynamic reconfiguration. We use fast and low-power SRAM blocks that are based on 10T SRAM cells. We have also laid out the various FPGA components in a 65-nm technology to evaluate the FPGA performance. We hide the dynamic reconfiguration delay behind the computation delay through the use of shadow SRAM cells. Experimental results show more than an order of magnitude improvement in logic density and 3.48X improvement in the area-delay product relative to a traditional baseline FPGA architecture that does not use the concept of logic folding. 2013-10-17T03:20:41Z 2019-12-06T20:12:20Z 2013-10-17T03:20:41Z 2019-12-06T20:12:20Z 2012 2012 Journal Article Lin, T. J., Zhang, W., & Jha, N. K. (2012). SRAM-based NATURE: A dynamically reconfigurable FPGA based on 10T low-power SRAMs. IEEE transactions on very large scale integration (VLSI) systems, 20(11), 2151-2156. 1063-8210 https://hdl.handle.net/10356/99851 http://hdl.handle.net/10220/16544 10.1109/TVLSI.2011.2169996 en IEEE transactions on very large scale integration (VLSI) systems © 2011 IEEE |
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DRNTU::Engineering::Computer science and engineering::Hardware::Logic design Jha, Niraj K. Lin, Ting-Jung Zhang, Wei SRAM-based NATURE: A dynamically reconfigurable FPGA based on 10T low-power SRAMs |
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We presented a hybrid CMOS/nanotechnology reconfigurable architecture (NATURE), earlier. It was based on CMOS logic and nano RAMs. It used the concept of temporal logic folding and fine-grain (e.g., cycle-level) dynamic reconfiguration to increase logic density by an order of magnitude. This dynamic reconfiguration is done intra-circuit rather than inter-circuit. However, the previous design of NATURE required fine-grained distribution of nano RAMs throughout the field-programmable gate array (FPGA) architecture. Since the fabrication process of nano RAMs is not mature yet, this prevents immediate exploitation of NATURE. In this paper, we present a NATURE architecture that is based on CMOS logic and CMOS SRAMs that are used for on-chip dynamic reconfiguration. We use fast and low-power SRAM blocks that are based on 10T SRAM cells. We have also laid out the various FPGA components in a 65-nm technology to evaluate the FPGA performance. We hide the dynamic reconfiguration delay behind the computation delay through the use of shadow SRAM cells. Experimental results show more than an order of magnitude improvement in logic density and 3.48X improvement in the area-delay product relative to a traditional baseline FPGA architecture that does not use the concept of logic folding. |
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School of Computer Engineering |
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School of Computer Engineering Jha, Niraj K. Lin, Ting-Jung Zhang, Wei |
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Jha, Niraj K. Lin, Ting-Jung Zhang, Wei |
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Jha, Niraj K. |
title |
SRAM-based NATURE: A dynamically reconfigurable FPGA based on 10T low-power SRAMs |
title_short |
SRAM-based NATURE: A dynamically reconfigurable FPGA based on 10T low-power SRAMs |
title_full |
SRAM-based NATURE: A dynamically reconfigurable FPGA based on 10T low-power SRAMs |
title_fullStr |
SRAM-based NATURE: A dynamically reconfigurable FPGA based on 10T low-power SRAMs |
title_full_unstemmed |
SRAM-based NATURE: A dynamically reconfigurable FPGA based on 10T low-power SRAMs |
title_sort |
sram-based nature: a dynamically reconfigurable fpga based on 10t low-power srams |
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2013 |
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https://hdl.handle.net/10356/99851 http://hdl.handle.net/10220/16544 |
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