Overlap clocking technique for 10 bit 50MHz 3V D/A converter

International Symposium on VLSI Technology, Systems, and Applications, Proceedings

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Main Authors: Bhatt, Ansuya, Singh, Raminder Jit, Tan, Khen-Sang
Other Authors: INSTITUTE OF MICROELECTRONICS
Format: Conference or Workshop Item
Published: 2014
Online Access:http://scholarbank.nus.edu.sg/handle/10635/112980
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Institution: National University of Singapore
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spelling sg-nus-scholar.10635-1129802024-11-15T02:42:54Z Overlap clocking technique for 10 bit 50MHz 3V D/A converter Bhatt, Ansuya Singh, Raminder Jit Tan, Khen-Sang INSTITUTE OF MICROELECTRONICS International Symposium on VLSI Technology, Systems, and Applications, Proceedings 361-364 220 2014-11-28T08:12:57Z 2014-11-28T08:12:57Z 1995 Conference Paper Bhatt, Ansuya,Singh, Raminder Jit,Tan, Khen-Sang (1995). Overlap clocking technique for 10 bit 50MHz 3V D/A converter. International Symposium on VLSI Technology, Systems, and Applications, Proceedings : 361-364. ScholarBank@NUS Repository. http://scholarbank.nus.edu.sg/handle/10635/112980 NOT_IN_WOS Scopus
institution National University of Singapore
building NUS Library
continent Asia
country Singapore
Singapore
content_provider NUS Library
collection ScholarBank@NUS
description International Symposium on VLSI Technology, Systems, and Applications, Proceedings
author2 INSTITUTE OF MICROELECTRONICS
author_facet INSTITUTE OF MICROELECTRONICS
Bhatt, Ansuya
Singh, Raminder Jit
Tan, Khen-Sang
format Conference or Workshop Item
author Bhatt, Ansuya
Singh, Raminder Jit
Tan, Khen-Sang
spellingShingle Bhatt, Ansuya
Singh, Raminder Jit
Tan, Khen-Sang
Overlap clocking technique for 10 bit 50MHz 3V D/A converter
author_sort Bhatt, Ansuya
title Overlap clocking technique for 10 bit 50MHz 3V D/A converter
title_short Overlap clocking technique for 10 bit 50MHz 3V D/A converter
title_full Overlap clocking technique for 10 bit 50MHz 3V D/A converter
title_fullStr Overlap clocking technique for 10 bit 50MHz 3V D/A converter
title_full_unstemmed Overlap clocking technique for 10 bit 50MHz 3V D/A converter
title_sort overlap clocking technique for 10 bit 50mhz 3v d/a converter
publishDate 2014
url http://scholarbank.nus.edu.sg/handle/10635/112980
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