Computing the soft error rate of a combinational logic circuit using parameterized descriptors

Computing the soft error rate of a combinational logic circuit using parameterized descriptors

10.1109/TCAD.2007.891036

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Bibliographic Details
Main Authors: Rao, R.R., Chopra, K., Blaauw, D.T., Sylvester, D.M.
Other Authors: ELECTRICAL & COMPUTER ENGINEERING
Format: Conference or Workshop Item
Published: 2016
Subjects:
Error analysis
Estimation
Simulation
Transient propagation
Online Access:http://scholarbank.nus.edu.sg/handle/10635/129493
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Institution: National University of Singapore

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http://scholarbank.nus.edu.sg/handle/10635/129493

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