Computing the soft error rate of a combinational logic circuit using parameterized descriptors

10.1109/TCAD.2007.891036

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Bibliographic Details
Main Authors:	Rao, R.R., Chopra, K., Blaauw, D.T., Sylvester, D.M.
Other Authors:	ELECTRICAL & COMPUTER ENGINEERING
Format:	Conference or Workshop Item
Published:	2016
Subjects:	Error analysis Estimation Simulation Transient propagation
Online Access:	http://scholarbank.nus.edu.sg/handle/10635/129493
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Institution:	National University of Singapore

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record_format	dspace
spelling	sg-nus-scholar.10635-1294932023-10-30T20:47:18Z Computing the soft error rate of a combinational logic circuit using parameterized descriptors Rao, R.R. Chopra, K. Blaauw, D.T. Sylvester, D.M. ELECTRICAL & COMPUTER ENGINEERING Error analysis Estimation Simulation Transient propagation 10.1109/TCAD.2007.891036 IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 26 3 468-478 ITCSD 2016-11-08T08:23:14Z 2016-11-08T08:23:14Z 2007-03 Conference Paper Rao, R.R., Chopra, K., Blaauw, D.T., Sylvester, D.M. (2007-03). Computing the soft error rate of a combinational logic circuit using parameterized descriptors. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 26 (3) : 468-478. ScholarBank@NUS Repository. https://doi.org/10.1109/TCAD.2007.891036 02780070 http://scholarbank.nus.edu.sg/handle/10635/129493 000244471200007 Scopus
institution	National University of Singapore
building	NUS Library
continent	Asia
country	Singapore Singapore
content_provider	NUS Library
collection	ScholarBank@NUS
topic	Error analysis Estimation Simulation Transient propagation
spellingShingle	Error analysis Estimation Simulation Transient propagation Rao, R.R. Chopra, K. Blaauw, D.T. Sylvester, D.M. Computing the soft error rate of a combinational logic circuit using parameterized descriptors
description	10.1109/TCAD.2007.891036
author2	ELECTRICAL & COMPUTER ENGINEERING
author_facet	ELECTRICAL & COMPUTER ENGINEERING Rao, R.R. Chopra, K. Blaauw, D.T. Sylvester, D.M.
format	Conference or Workshop Item
author	Rao, R.R. Chopra, K. Blaauw, D.T. Sylvester, D.M.
author_sort	Rao, R.R.
title	Computing the soft error rate of a combinational logic circuit using parameterized descriptors
title_short	Computing the soft error rate of a combinational logic circuit using parameterized descriptors
title_full	Computing the soft error rate of a combinational logic circuit using parameterized descriptors
title_fullStr	Computing the soft error rate of a combinational logic circuit using parameterized descriptors
title_full_unstemmed	Computing the soft error rate of a combinational logic circuit using parameterized descriptors
title_sort	computing the soft error rate of a combinational logic circuit using parameterized descriptors
publishDate	2016
url	http://scholarbank.nus.edu.sg/handle/10635/129493
_version_	1781790663708246016

Computing the soft error rate of a combinational logic circuit using parameterized descriptors

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