Automatic mapping of statechart into verilog

Master's

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Bibliographic Details
Main Author:	TRAN VU VIET ANH
Other Authors:	COMPUTER SCIENCE
Format:	Theses and Dissertations
Language:	English
Published:	2010
Subjects:	Statecharts, Verilog, embedded system, hardware/software co-specification
Online Access:	http://scholarbank.nus.edu.sg/handle/10635/13956
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Institution:	National University of Singapore
Language:	English

id	sg-nus-scholar.10635-13956
record_format	dspace
spelling	sg-nus-scholar.10635-139562015-08-17T19:43:02Z Automatic mapping of statechart into verilog TRAN VU VIET ANH COMPUTER SCIENCE CHIN WEI NGAN Statecharts, Verilog, embedded system, hardware/software co-specification Master's MASTER OF SCIENCE 2010-04-08T10:38:27Z 2010-04-08T10:38:27Z 2004-05-26 Thesis TRAN VU VIET ANH (2004-05-26). Automatic mapping of statechart into verilog. ScholarBank@NUS Repository. http://scholarbank.nus.edu.sg/handle/10635/13956 NOT_IN_WOS en
institution	National University of Singapore
building	NUS Library
country	Singapore
collection	ScholarBank@NUS
language	English
topic	Statecharts, Verilog, embedded system, hardware/software co-specification
spellingShingle	Statecharts, Verilog, embedded system, hardware/software co-specification TRAN VU VIET ANH Automatic mapping of statechart into verilog
description	Master's
author2	COMPUTER SCIENCE
author_facet	COMPUTER SCIENCE TRAN VU VIET ANH
format	Theses and Dissertations
author	TRAN VU VIET ANH
author_sort	TRAN VU VIET ANH
title	Automatic mapping of statechart into verilog
title_short	Automatic mapping of statechart into verilog
title_full	Automatic mapping of statechart into verilog
title_fullStr	Automatic mapping of statechart into verilog
title_full_unstemmed	Automatic mapping of statechart into verilog
title_sort	automatic mapping of statechart into verilog
publishDate	2010
url	http://scholarbank.nus.edu.sg/handle/10635/13956
_version_	1681078945674428416

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