Design of a fully digital multi-level decision feedback equalization chip

Master's

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Bibliographic Details
Main Author:	XIE JIANG
Other Authors:	ELECTRICAL & COMPUTER ENGINEERING
Format:	Theses and Dissertations
Language:	English
Published:	2010
Subjects:	MDFE, Decision Feedback, Equalizer, Read Channel, ASIC
Online Access:	http://scholarbank.nus.edu.sg/handle/10635/14674
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Institution:	National University of Singapore
Language:	English

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record_format	dspace
spelling	sg-nus-scholar.10635-146742024-10-26T07:43:14Z Design of a fully digital multi-level decision feedback equalization chip XIE JIANG ELECTRICAL & COMPUTER ENGINEERING XU YONG-PING MDFE, Decision Feedback, Equalizer, Read Channel, ASIC Master's MASTER OF ENGINEERING 2010-04-08T10:45:35Z 2010-04-08T10:45:35Z 2005-03-15 Thesis XIE JIANG (2005-03-15). Design of a fully digital multi-level decision feedback equalization chip. ScholarBank@NUS Repository. http://scholarbank.nus.edu.sg/handle/10635/14674 NOT_IN_WOS en
institution	National University of Singapore
building	NUS Library
continent	Asia
country	Singapore Singapore
content_provider	NUS Library
collection	ScholarBank@NUS
language	English
topic	MDFE, Decision Feedback, Equalizer, Read Channel, ASIC
spellingShingle	MDFE, Decision Feedback, Equalizer, Read Channel, ASIC XIE JIANG Design of a fully digital multi-level decision feedback equalization chip
description	Master's
author2	ELECTRICAL & COMPUTER ENGINEERING
author_facet	ELECTRICAL & COMPUTER ENGINEERING XIE JIANG
format	Theses and Dissertations
author	XIE JIANG
author_sort	XIE JIANG
title	Design of a fully digital multi-level decision feedback equalization chip
title_short	Design of a fully digital multi-level decision feedback equalization chip
title_full	Design of a fully digital multi-level decision feedback equalization chip
title_fullStr	Design of a fully digital multi-level decision feedback equalization chip
title_full_unstemmed	Design of a fully digital multi-level decision feedback equalization chip
title_sort	design of a fully digital multi-level decision feedback equalization chip
publishDate	2010
url	http://scholarbank.nus.edu.sg/handle/10635/14674
_version_	1821219893608972288

Design of a fully digital multi-level decision feedback equalization chip

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