Instruction and data cache modeling for timing analysis in real-time systems
Master's
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sg-nus-scholar.10635-166302017-10-21T06:01:46Z Instruction and data cache modeling for timing analysis in real-time systems LI YANHUI ELECTRICAL & COMPUTER ENGINEERING HA YAJUN TAY TENG TIOW WCET, Cache, Real-time System, input-dependent data access, NP-completeness, System Performance Master's MASTER OF ENGINEERING 2010-04-08T11:07:15Z 2010-04-08T11:07:15Z 2009-02-09 Thesis LI YANHUI (2009-02-09). Instruction and data cache modeling for timing analysis in real-time systems. ScholarBank@NUS Repository. http://scholarbank.nus.edu.sg/handle/10635/16630 NOT_IN_WOS en |
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National University of Singapore |
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NUS Library |
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Singapore |
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ScholarBank@NUS |
language |
English |
topic |
WCET, Cache, Real-time System, input-dependent data access, NP-completeness, System Performance |
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WCET, Cache, Real-time System, input-dependent data access, NP-completeness, System Performance LI YANHUI Instruction and data cache modeling for timing analysis in real-time systems |
description |
Master's |
author2 |
ELECTRICAL & COMPUTER ENGINEERING |
author_facet |
ELECTRICAL & COMPUTER ENGINEERING LI YANHUI |
format |
Theses and Dissertations |
author |
LI YANHUI |
author_sort |
LI YANHUI |
title |
Instruction and data cache modeling for timing analysis in real-time systems |
title_short |
Instruction and data cache modeling for timing analysis in real-time systems |
title_full |
Instruction and data cache modeling for timing analysis in real-time systems |
title_fullStr |
Instruction and data cache modeling for timing analysis in real-time systems |
title_full_unstemmed |
Instruction and data cache modeling for timing analysis in real-time systems |
title_sort |
instruction and data cache modeling for timing analysis in real-time systems |
publishDate |
2010 |
url |
http://scholarbank.nus.edu.sg/handle/10635/16630 |
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1681079395118219264 |