Instruction and data cache modeling for timing analysis in real-time systems
Master's
Saved in:
Main Author: | LI YANHUI |
---|---|
Other Authors: | ELECTRICAL & COMPUTER ENGINEERING |
Format: | Theses and Dissertations |
Language: | English |
Published: |
2010
|
Subjects: | |
Online Access: | http://scholarbank.nus.edu.sg/handle/10635/16630 |
Tags: |
Add Tag
No Tags, Be the first to tag this record!
|
Institution: | National University of Singapore |
Language: | English |
Similar Items
-
Instruction Cache Optimizations in Embedded Real-Time Systems
by: DING HUPING
Published: (2014) -
Integrated instruction cache analysis and locking in multitasking real-time systems
by: Ding, H., et al.
Published: (2014) -
Memory Optimizations for Time-Predictable Embedded Software
by: VIVY SUHENDRA
Published: (2010) -
WCET-centric partial instruction cache locking
by: Ding, H., et al.
Published: (2013) -
Timing analysis of concurrent programs running on shared cache multi-cores
by: Liang, Y., et al.
Published: (2013)