Subthreshold quasi-delay-insensitive circuit designs

Master's

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Bibliographic Details
Main Author: CHANG XIAOFEI
Other Authors: ELECTRICAL & COMPUTER ENGINEERING
Format: Theses and Dissertations
Language:English
Published: 2011
Subjects:
Online Access:http://scholarbank.nus.edu.sg/handle/10635/21142
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Institution: National University of Singapore
Language: English
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spelling sg-nus-scholar.10635-211422017-10-21T07:57:48Z Subthreshold quasi-delay-insensitive circuit designs CHANG XIAOFEI ELECTRICAL & COMPUTER ENGINEERING LIAN YONG asynchronous,low-power,filter,subthreshold,delay-insensitive Master's MASTER OF ENGINEERING 2011-04-11T18:00:07Z 2011-04-11T18:00:07Z 2010-06-10 Thesis CHANG XIAOFEI (2010-06-10). Subthreshold quasi-delay-insensitive circuit designs. ScholarBank@NUS Repository. http://scholarbank.nus.edu.sg/handle/10635/21142 NOT_IN_WOS en
institution National University of Singapore
building NUS Library
country Singapore
collection ScholarBank@NUS
language English
topic asynchronous,low-power,filter,subthreshold,delay-insensitive
spellingShingle asynchronous,low-power,filter,subthreshold,delay-insensitive
CHANG XIAOFEI
Subthreshold quasi-delay-insensitive circuit designs
description Master's
author2 ELECTRICAL & COMPUTER ENGINEERING
author_facet ELECTRICAL & COMPUTER ENGINEERING
CHANG XIAOFEI
format Theses and Dissertations
author CHANG XIAOFEI
author_sort CHANG XIAOFEI
title Subthreshold quasi-delay-insensitive circuit designs
title_short Subthreshold quasi-delay-insensitive circuit designs
title_full Subthreshold quasi-delay-insensitive circuit designs
title_fullStr Subthreshold quasi-delay-insensitive circuit designs
title_full_unstemmed Subthreshold quasi-delay-insensitive circuit designs
title_sort subthreshold quasi-delay-insensitive circuit designs
publishDate 2011
url http://scholarbank.nus.edu.sg/handle/10635/21142
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