Subthreshold quasi-delay-insensitive circuit designs
Master's
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sg-nus-scholar.10635-211422017-10-21T07:57:48Z Subthreshold quasi-delay-insensitive circuit designs CHANG XIAOFEI ELECTRICAL & COMPUTER ENGINEERING LIAN YONG asynchronous,low-power,filter,subthreshold,delay-insensitive Master's MASTER OF ENGINEERING 2011-04-11T18:00:07Z 2011-04-11T18:00:07Z 2010-06-10 Thesis CHANG XIAOFEI (2010-06-10). Subthreshold quasi-delay-insensitive circuit designs. ScholarBank@NUS Repository. http://scholarbank.nus.edu.sg/handle/10635/21142 NOT_IN_WOS en |
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asynchronous,low-power,filter,subthreshold,delay-insensitive |
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asynchronous,low-power,filter,subthreshold,delay-insensitive CHANG XIAOFEI Subthreshold quasi-delay-insensitive circuit designs |
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Master's |
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ELECTRICAL & COMPUTER ENGINEERING |
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ELECTRICAL & COMPUTER ENGINEERING CHANG XIAOFEI |
format |
Theses and Dissertations |
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CHANG XIAOFEI |
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CHANG XIAOFEI |
title |
Subthreshold quasi-delay-insensitive circuit designs |
title_short |
Subthreshold quasi-delay-insensitive circuit designs |
title_full |
Subthreshold quasi-delay-insensitive circuit designs |
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Subthreshold quasi-delay-insensitive circuit designs |
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Subthreshold quasi-delay-insensitive circuit designs |
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subthreshold quasi-delay-insensitive circuit designs |
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2011 |
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http://scholarbank.nus.edu.sg/handle/10635/21142 |
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