50-250MHZ ?S DLL for Clock Synchronization

Ph.D

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Bibliographic Details
Main Author:	CHENG SAN JEOW
Other Authors:	ELECTRICAL & COMPUTER ENGINEERING
Format:	Theses and Dissertations
Language:	English
Published:	2012
Subjects:	delta-sigma, DLL, clock synchronization, CMOS, jitter, resolution
Online Access:	http://scholarbank.nus.edu.sg/handle/10635/31648
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Institution:	National University of Singapore
Language:	English

id	sg-nus-scholar.10635-31648
record_format	dspace
spelling	sg-nus-scholar.10635-316482015-01-17T03:38:45Z 50-250MHZ ?S DLL for Clock Synchronization CHENG SAN JEOW ELECTRICAL & COMPUTER ENGINEERING HENG CHUN HUAT delta-sigma, DLL, clock synchronization, CMOS, jitter, resolution Ph.D DOCTOR OF PHILOSOPHY 2012-03-31T18:02:25Z 2012-03-31T18:02:25Z 2011-04-14 Thesis CHENG SAN JEOW (2011-04-14). 50-250MHZ ?S DLL for Clock Synchronization. ScholarBank@NUS Repository. http://scholarbank.nus.edu.sg/handle/10635/31648 NOT_IN_WOS en
institution	National University of Singapore
building	NUS Library
country	Singapore
collection	ScholarBank@NUS
language	English
topic	delta-sigma, DLL, clock synchronization, CMOS, jitter, resolution
spellingShingle	delta-sigma, DLL, clock synchronization, CMOS, jitter, resolution CHENG SAN JEOW 50-250MHZ ?S DLL for Clock Synchronization
description	Ph.D
author2	ELECTRICAL & COMPUTER ENGINEERING
author_facet	ELECTRICAL & COMPUTER ENGINEERING CHENG SAN JEOW
format	Theses and Dissertations
author	CHENG SAN JEOW
author_sort	CHENG SAN JEOW
title	50-250MHZ ?S DLL for Clock Synchronization
title_short	50-250MHZ ?S DLL for Clock Synchronization
title_full	50-250MHZ ?S DLL for Clock Synchronization
title_fullStr	50-250MHZ ?S DLL for Clock Synchronization
title_full_unstemmed	50-250MHZ ?S DLL for Clock Synchronization
title_sort	50-250mhz ?s dll for clock synchronization
publishDate	2012
url	http://scholarbank.nus.edu.sg/handle/10635/31648
_version_	1681081112770641920

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