Fault simulator based on a hardware-in-The-loop technique

10.1109/TSMCC.2012.2182992

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Main Authors: Huang, S., Tan, K.K.
Other Authors: ELECTRICAL & COMPUTER ENGINEERING
Format: Article
Published: 2014
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Online Access:http://scholarbank.nus.edu.sg/handle/10635/56026
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Institution: National University of Singapore
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spelling sg-nus-scholar.10635-560262023-10-26T08:34:40Z Fault simulator based on a hardware-in-The-loop technique Huang, S. Tan, K.K. ELECTRICAL & COMPUTER ENGINEERING Failure hardware-in-The-loop (HIL) simulation nonlinear systems real-time control 10.1109/TSMCC.2012.2182992 IEEE Transactions on Systems, Man and Cybernetics Part C: Applications and Reviews 42 6 1135-1139 ITCRF 2014-06-17T02:49:52Z 2014-06-17T02:49:52Z 2012 Article Huang, S., Tan, K.K. (2012). Fault simulator based on a hardware-in-The-loop technique. IEEE Transactions on Systems, Man and Cybernetics Part C: Applications and Reviews 42 (6) : 1135-1139. ScholarBank@NUS Repository. https://doi.org/10.1109/TSMCC.2012.2182992 10946977 http://scholarbank.nus.edu.sg/handle/10635/56026 000310139700030 Scopus
institution National University of Singapore
building NUS Library
continent Asia
country Singapore
Singapore
content_provider NUS Library
collection ScholarBank@NUS
topic Failure
hardware-in-The-loop (HIL) simulation
nonlinear systems
real-time control
spellingShingle Failure
hardware-in-The-loop (HIL) simulation
nonlinear systems
real-time control
Huang, S.
Tan, K.K.
Fault simulator based on a hardware-in-The-loop technique
description 10.1109/TSMCC.2012.2182992
author2 ELECTRICAL & COMPUTER ENGINEERING
author_facet ELECTRICAL & COMPUTER ENGINEERING
Huang, S.
Tan, K.K.
format Article
author Huang, S.
Tan, K.K.
author_sort Huang, S.
title Fault simulator based on a hardware-in-The-loop technique
title_short Fault simulator based on a hardware-in-The-loop technique
title_full Fault simulator based on a hardware-in-The-loop technique
title_fullStr Fault simulator based on a hardware-in-The-loop technique
title_full_unstemmed Fault simulator based on a hardware-in-The-loop technique
title_sort fault simulator based on a hardware-in-the-loop technique
publishDate 2014
url http://scholarbank.nus.edu.sg/handle/10635/56026
_version_ 1781781100045008896