An area-efficient timing-driven routing algorithm for scalable FPGAs with time-multiplexed interconnects

An area-efficient timing-driven routing algorithm for scalable FPGAs with time-multiplexed interconnects

10.1109/FCCM.2008.28

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Bibliographic Details
Main Authors: Liu, H., Chen, X., Ha, Y.
Other Authors: ELECTRICAL & COMPUTER ENGINEERING
Format: Conference or Workshop Item
Published: 2014
Online Access:http://scholarbank.nus.edu.sg/handle/10635/69286
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Institution: National University of Singapore
Description
Summary:10.1109/FCCM.2008.28

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