An automated, efficient and static bit-width optimization methodology towards maximum bit-width-to-error tradeoff with affine arithmetic model

Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

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Bibliographic Details
Main Authors:	Pu, Y., Ha, Y.
Other Authors:	ELECTRICAL & COMPUTER ENGINEERING
Format:	Conference or Workshop Item
Published:	2014
Online Access:	http://scholarbank.nus.edu.sg/handle/10635/69293
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Institution:	National University of Singapore

id	sg-nus-scholar.10635-69293
record_format	dspace
spelling	sg-nus-scholar.10635-692932015-01-16T14:54:13Z An automated, efficient and static bit-width optimization methodology towards maximum bit-width-to-error tradeoff with affine arithmetic model Pu, Y. Ha, Y. ELECTRICAL & COMPUTER ENGINEERING Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC 2006 886-891 2014-06-19T02:59:02Z 2014-06-19T02:59:02Z 2006 Conference Paper Pu, Y.,Ha, Y. (2006). An automated, efficient and static bit-width optimization methodology towards maximum bit-width-to-error tradeoff with affine arithmetic model. Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC 2006 : 886-891. ScholarBank@NUS Repository. 0780394518 http://scholarbank.nus.edu.sg/handle/10635/69293 NOT_IN_WOS Scopus
institution	National University of Singapore
building	NUS Library
country	Singapore
collection	ScholarBank@NUS
description	Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC
author2	ELECTRICAL & COMPUTER ENGINEERING
author_facet	ELECTRICAL & COMPUTER ENGINEERING Pu, Y. Ha, Y.
format	Conference or Workshop Item
author	Pu, Y. Ha, Y.
spellingShingle	Pu, Y. Ha, Y. An automated, efficient and static bit-width optimization methodology towards maximum bit-width-to-error tradeoff with affine arithmetic model
author_sort	Pu, Y.
title	An automated, efficient and static bit-width optimization methodology towards maximum bit-width-to-error tradeoff with affine arithmetic model
title_short	An automated, efficient and static bit-width optimization methodology towards maximum bit-width-to-error tradeoff with affine arithmetic model
title_full	An automated, efficient and static bit-width optimization methodology towards maximum bit-width-to-error tradeoff with affine arithmetic model
title_fullStr	An automated, efficient and static bit-width optimization methodology towards maximum bit-width-to-error tradeoff with affine arithmetic model
title_full_unstemmed	An automated, efficient and static bit-width optimization methodology towards maximum bit-width-to-error tradeoff with affine arithmetic model
title_sort	automated, efficient and static bit-width optimization methodology towards maximum bit-width-to-error tradeoff with affine arithmetic model
publishDate	2014
url	http://scholarbank.nus.edu.sg/handle/10635/69293
_version_	1681086987192238080

An automated, efficient and static bit-width optimization methodology towards maximum bit-width-to-error tradeoff with affine arithmetic model

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