An automated, efficient and static bit-width optimization methodology towards maximum bit-width-to-error tradeoff with affine arithmetic model
Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC
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Main Authors: | Pu, Y., Ha, Y. |
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Other Authors: | ELECTRICAL & COMPUTER ENGINEERING |
Format: | Conference or Workshop Item |
Published: |
2014
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Online Access: | http://scholarbank.nus.edu.sg/handle/10635/69293 |
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Institution: | National University of Singapore |
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