A novel interpolation approach for reducing clock-rate in multilevel decision feedback equalization detectors

10.1109/20.908407

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Bibliographic Details
Main Authors:	Mathew, G., Yuan Xing Lee, Farhang-Boroujeny, B., Mutoh, H., Jian Jiang Wang
Other Authors:	ELECTRICAL ENGINEERING
Format:	Conference or Workshop Item
Published:	2014
Subjects:	Clock-rate reduction Interpolation Magnetic recording Multilevel decision feedback equalization Timing recovery
Online Access:	http://scholarbank.nus.edu.sg/handle/10635/72447
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Institution:	National University of Singapore

id	sg-nus-scholar.10635-72447
record_format	dspace
spelling	sg-nus-scholar.10635-724472023-10-30T21:06:54Z A novel interpolation approach for reducing clock-rate in multilevel decision feedback equalization detectors Mathew, G. Yuan Xing Lee Farhang-Boroujeny, B. Mutoh, H. Jian Jiang Wang ELECTRICAL ENGINEERING Clock-rate reduction Interpolation Magnetic recording Multilevel decision feedback equalization Timing recovery 10.1109/20.908407 IEEE Transactions on Magnetics 36 5 II 3866-3878 IEMGA 2014-06-19T05:08:09Z 2014-06-19T05:08:09Z 2000-09 Conference Paper Mathew, G., Yuan Xing Lee, Farhang-Boroujeny, B., Mutoh, H., Jian Jiang Wang (2000-09). A novel interpolation approach for reducing clock-rate in multilevel decision feedback equalization detectors. IEEE Transactions on Magnetics 36 (5 II) : 3866-3878. ScholarBank@NUS Repository. https://doi.org/10.1109/20.908407 00189464 http://scholarbank.nus.edu.sg/handle/10635/72447 000167371900016 Scopus
institution	National University of Singapore
building	NUS Library
continent	Asia
country	Singapore Singapore
content_provider	NUS Library
collection	ScholarBank@NUS
topic	Clock-rate reduction Interpolation Magnetic recording Multilevel decision feedback equalization Timing recovery
spellingShingle	Clock-rate reduction Interpolation Magnetic recording Multilevel decision feedback equalization Timing recovery Mathew, G. Yuan Xing Lee Farhang-Boroujeny, B. Mutoh, H. Jian Jiang Wang A novel interpolation approach for reducing clock-rate in multilevel decision feedback equalization detectors
description	10.1109/20.908407
author2	ELECTRICAL ENGINEERING
author_facet	ELECTRICAL ENGINEERING Mathew, G. Yuan Xing Lee Farhang-Boroujeny, B. Mutoh, H. Jian Jiang Wang
format	Conference or Workshop Item
author	Mathew, G. Yuan Xing Lee Farhang-Boroujeny, B. Mutoh, H. Jian Jiang Wang
author_sort	Mathew, G.
title	A novel interpolation approach for reducing clock-rate in multilevel decision feedback equalization detectors
title_short	A novel interpolation approach for reducing clock-rate in multilevel decision feedback equalization detectors
title_full	A novel interpolation approach for reducing clock-rate in multilevel decision feedback equalization detectors
title_fullStr	A novel interpolation approach for reducing clock-rate in multilevel decision feedback equalization detectors
title_full_unstemmed	A novel interpolation approach for reducing clock-rate in multilevel decision feedback equalization detectors
title_sort	novel interpolation approach for reducing clock-rate in multilevel decision feedback equalization detectors
publishDate	2014
url	http://scholarbank.nus.edu.sg/handle/10635/72447
_version_	1781783260902195200

A novel interpolation approach for reducing clock-rate in multilevel decision feedback equalization detectors

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