Optimum partitioning problem for rectilinear VLSI layout

IEE Proceedings: Computers and Digital Techniques

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Bibliographic Details
Main Authors:	Ku, L.-P., Leong, H.W.
Other Authors:	INFORMATION SYSTEMS & COMPUTER SCIENCE
Format:	Article
Published:	2014
Subjects:	Layout partitioning VLSI
Online Access:	http://scholarbank.nus.edu.sg/handle/10635/99369
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Institution:	National University of Singapore

id	sg-nus-scholar.10635-99369
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spelling	sg-nus-scholar.10635-993692015-02-22T20:37:23Z Optimum partitioning problem for rectilinear VLSI layout Ku, L.-P. Leong, H.W. INFORMATION SYSTEMS & COMPUTER SCIENCE Layout partitioning VLSI IEE Proceedings: Computers and Digital Techniques 144 3 155-162 ICDTE 2014-10-27T06:03:28Z 2014-10-27T06:03:28Z 1997 Article Ku, L.-P.,Leong, H.W. (1997). Optimum partitioning problem for rectilinear VLSI layout. IEE Proceedings: Computers and Digital Techniques 144 (3) : 155-162. ScholarBank@NUS Repository. 13502387 http://scholarbank.nus.edu.sg/handle/10635/99369 NOT_IN_WOS Scopus
institution	National University of Singapore
building	NUS Library
country	Singapore
collection	ScholarBank@NUS
topic	Layout partitioning VLSI
spellingShingle	Layout partitioning VLSI Ku, L.-P. Leong, H.W. Optimum partitioning problem for rectilinear VLSI layout
description	IEE Proceedings: Computers and Digital Techniques
author2	INFORMATION SYSTEMS & COMPUTER SCIENCE
author_facet	INFORMATION SYSTEMS & COMPUTER SCIENCE Ku, L.-P. Leong, H.W.
format	Article
author	Ku, L.-P. Leong, H.W.
author_sort	Ku, L.-P.
title	Optimum partitioning problem for rectilinear VLSI layout
title_short	Optimum partitioning problem for rectilinear VLSI layout
title_full	Optimum partitioning problem for rectilinear VLSI layout
title_fullStr	Optimum partitioning problem for rectilinear VLSI layout
title_full_unstemmed	Optimum partitioning problem for rectilinear VLSI layout
title_sort	optimum partitioning problem for rectilinear vlsi layout
publishDate	2014
url	http://scholarbank.nus.edu.sg/handle/10635/99369
_version_	1681092177483005952

Optimum partitioning problem for rectilinear VLSI layout

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