Symbolic model-checking of stateful timed CSP using BDD and digitization
Stateful Timed CSP has been recently proposed to model (and verify) hierarchical real-time systems. It is an expressive modeling language which combines data structure/operations, complicated control flows (modeled using compositional process operators adopted from Timed CSP), and real-time requirem...
Saved in:
Main Authors: | NGUYEN, Truong Khanh, SUN, Jun, LIU, Yang, DONG, Jin Song |
---|---|
Format: | text |
Language: | English |
Published: |
Institutional Knowledge at Singapore Management University
2012
|
Subjects: | |
Online Access: | https://ink.library.smu.edu.sg/sis_research/5024 https://ink.library.smu.edu.sg/context/sis_research/article/6027/viewcontent/symbolic.pdf |
Tags: |
Add Tag
No Tags, Be the first to tag this record!
|
Institution: | Singapore Management University |
Language: | English |
Similar Items
-
Improved BDD-based discrete analysis of timed systems
by: NGUYEN, Truong Khanh, et al.
Published: (2012) -
Fair model checking with process counter abstraction
by: SUN, Jun, et al.
Published: (2009) -
PRTS: An approach for model checking probabilistic real-time hierarchical systems
by: SUN, Jun, et al.
Published: (2011) -
PAT: Towards flexible verification under fairness
by: SUN, Jun, et al.
Published: (2009) -
Scalable multi-core model checking fairness enhanced systems
by: LIU, Yang, et al.
Published: (2009)