Visilence: An interactive visualization tool for error resilience analysis
Soft errors have become one of the major concerns for HPC applications, as those errors can result in seriously corrupted outcomes, such as silent data corruptions (SDCs). Prior studies on error resilience have studied the robustness of HPC applications. However, it is still difficult for program de...
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| Main Authors: | , , |
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| Format: | text |
| Language: | English |
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Institutional Knowledge at Singapore Management University
2021
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| Subjects: | |
| Online Access: | https://ink.library.smu.edu.sg/sis_research/6844 https://ink.library.smu.edu.sg/context/sis_research/article/7847/viewcontent/21_IEEEVIS_Poster_visilence.pdf |
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| Institution: | Singapore Management University |
| Language: | English |
| Summary: | Soft errors have become one of the major concerns for HPC applications, as those errors can result in seriously corrupted outcomes, such as silent data corruptions (SDCs). Prior studies on error resilience have studied the robustness of HPC applications. However, it is still difficult for program developers to identify potential vulnerability to soft errors. In this paper, we present Visilence, a novel visualization tool to visually analyze error vulnerability based on the control-flow graph generated from HPC applications. Visilence efficiently visualizes the affected program states under injected errors and presents the visual analysis of the most vulnerable parts of an application. We demonstrate the effectiveness of Visilence through a case study. |
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