A 1 GHz CMOS analog equalizer for perpendicular magnetic recording
This paper describes the design of a CMOS analog discrete-time equalizer for perpendicular magnetic recording (PMR) read channel. In this design the structure of analog FIR filter that places rotating switch matrix between DAC and multiplier has been proposed. It reduces an accumulative switching er...
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th-mahidol.289832018-09-24T15:59:11Z A 1 GHz CMOS analog equalizer for perpendicular magnetic recording Sukarasut Meksiri Kasin Vichienchom Decha Wilairat King Mongkut's Institute of Technology Ladkrabang Mahidol University Computer Science Engineering This paper describes the design of a CMOS analog discrete-time equalizer for perpendicular magnetic recording (PMR) read channel. In this design the structure of analog FIR filter that places rotating switch matrix between DAC and multiplier has been proposed. It reduces an accumulative switching error in analog samples due to rotating switch matrix. A 7-tap filter circuit based on GPR2 target was designed and simulated using TSMC 0.18 μm CMOS process parameters. Simulation results show good agreement with the results of the system level simulation. At 1 GHz sampling frequency the equalizer dissipates 1.5 mW. ©2010 IEEE. 2018-09-24T08:56:31Z 2018-09-24T08:56:31Z 2010-12-01 Conference Paper IEEE Region 10 Annual International Conference, Proceedings/TENCON. (2010), 1521-1524 10.1109/TENCON.2010.5686144 2-s2.0-79951639183 https://repository.li.mahidol.ac.th/handle/123456789/28983 Mahidol University SCOPUS https://www.scopus.com/inward/record.uri?partnerID=HzOxMe3b&scp=79951639183&origin=inward |
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Computer Science Engineering |
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Computer Science Engineering Sukarasut Meksiri Kasin Vichienchom Decha Wilairat A 1 GHz CMOS analog equalizer for perpendicular magnetic recording |
| description |
This paper describes the design of a CMOS analog discrete-time equalizer for perpendicular magnetic recording (PMR) read channel. In this design the structure of analog FIR filter that places rotating switch matrix between DAC and multiplier has been proposed. It reduces an accumulative switching error in analog samples due to rotating switch matrix. A 7-tap filter circuit based on GPR2 target was designed and simulated using TSMC 0.18 μm CMOS process parameters. Simulation results show good agreement with the results of the system level simulation. At 1 GHz sampling frequency the equalizer dissipates 1.5 mW. ©2010 IEEE. |
| author2 |
King Mongkut's Institute of Technology Ladkrabang |
| author_facet |
King Mongkut's Institute of Technology Ladkrabang Sukarasut Meksiri Kasin Vichienchom Decha Wilairat |
| format |
Conference or Workshop Item |
| author |
Sukarasut Meksiri Kasin Vichienchom Decha Wilairat |
| author_sort |
Sukarasut Meksiri |
| title |
A 1 GHz CMOS analog equalizer for perpendicular magnetic recording |
| title_short |
A 1 GHz CMOS analog equalizer for perpendicular magnetic recording |
| title_full |
A 1 GHz CMOS analog equalizer for perpendicular magnetic recording |
| title_fullStr |
A 1 GHz CMOS analog equalizer for perpendicular magnetic recording |
| title_full_unstemmed |
A 1 GHz CMOS analog equalizer for perpendicular magnetic recording |
| title_sort |
1 ghz cmos analog equalizer for perpendicular magnetic recording |
| publishDate |
2018 |
| url |
https://repository.li.mahidol.ac.th/handle/123456789/28983 |
| _version_ |
1763488949542584320 |