RELIABILITY-EVALUATION OF NANOSCALE CIRCUIT DESIGN USING BAYESIAN NETWORKS

by KHALID, USMAN
Published 2012

Highly noise-tolerant design of digital logic gates using Markov Random Field modelling

by Anwer, Janhanzeb, Khalid, Usman, Hamid, Nor Hisham, Asirvadam , Vijanth Sagayan
Published 2010

Joint and marginal probability analyses of Markov Random Field networks for digital logic circuits

by Anwer, Jahanzeb, Khalid, Usman, Singh, Narinderjit, Hamid, Nor H., Asirvadam, Vijanth S.
Published 2010

Highly noise-tolerant design of digital logic gates using Markov Random Field modelling

by Anwer, Janhanzeb, Khalid, Usman, Hamid, Nor Hisham, Asirvadam , Vijanth Sagayan, Singh, Narenderjit
Published 2010