RISC PROCESSOR NICCOLO32 DESIGN AND IMPLEMENTATION

• Main Author: OCTAVIANUS (NIM 23204050), KAREL
• Format: Theses
• Language: Indonesia
• Online Access: https://digilib.itb.ac.id/gdl/view/10751
• Institution: Institut Teknologi Bandung

<p align="justify">Reduced instruction set computer (RISC) is a computer architecture that reduces chip complexity by using simpler instructions, which allows high speed operations. RISC keeps instruction size constant, and bans the indirect addressing.<p align="justify"><p>Compared to CISC, RISC has some advantages. RISC instructions require only one clock cycle, thus, RISC does not require large area used for instruction processing. RISC allows pipelining due to one instruction per cycle. RISC applies load/store architecture. Only load and store access memory. This reduces the amount of work that the computer must perform. RISC can be easily integrated in System on Chip design.<p align="justify"><p>In this thesis, a SPARC V8 RISC processor will be designed and implemented. This processor is named RISC processor Niccolo32. Design is started with choosing instruction. Register transfer notation (RTN) is then made for each instruction chosen. Based on RTN, datapath is designed. Datapath must support all instructions. Datapath is controlled by control unit using control signals.<p align="justify"><p>Niccolo32 design is simulated using modelsim. Test vector is fed into the system to ensure system functionality. SPARC assembly, which is generated by compiling C language listing program, is chosen to be the test vector.<p align="justify"><p>The last step of Niccolo32 implementation is synthesize and chip layout using design analyzer and Astro, synopsys CAD tools, with 0,18 µm technology file. Chip layout implementation results maximum clock frequency of 31,46 Mhz and chip area of 0,668 mm2.