A STUDY OF QUANTUM TUNNELING PHENOMENA AT SHARP-SHAPED FLOATING GATE STRUCTURE ON FLASH MEMORY DEVICE
A study of electrical characteristic of the sharp-shaped floating gate on flash memory cell has been conducted. Specifically, we aim to study quantum tunneling phenomena. It begin with simple electrostatic modeling from which we moved to transmission coefficient calculation using transfer matrix met...
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| Format: | Theses |
| Language: | Indonesia |
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| Online Access: | https://digilib.itb.ac.id/gdl/view/27525 |
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| Institution: | Institut Teknologi Bandung |
| Language: | Indonesia |
| Summary: | A study of electrical characteristic of the sharp-shaped floating gate on flash memory cell has been conducted. Specifically, we aim to study quantum tunneling phenomena. It begin with simple electrostatic modeling from which we moved to transmission coefficient calculation using transfer matrix method, we then proceed to tunnel current density calculation. Last, a simulation regarding sharp-shaped floating gate fabrication was carried by simulating the LOCOS technique using several deposition parameters. Analytical study of sharp electrode shows a barrier profile that are very similar to those generated using Sentaurus DeviceTM numerical tools from Synopsys, especially for sharp electrode with a wide opening angle ???? (>45?). While for smaller ???? (18??20?), the analytical result only shows a minor difference with its numerical counterpart. However, this minor difference were quickly vanish at high voltage regime (10-12 Volt) which was the flash memory working voltage. A transfer matrix method applied to calculate transmission cofficient gives a different values for different path, with the highest one being the straight path perpendicular to sharp-tip structure. A quick inspection on barrier profile along horizontal line reveal that the barrier profile has its minimum value exactly at the perpendicular path. Thus, we can explain the perpendicular line as the most probable path in term of barrier profile. The tunnel current density calculation shows that the sharp-structured elecrode gives a significantly higher current density than the planar one. The floating gate fabricaton process by the LOCOS technique was simulated using Sentaurus Process. By variating oxidation temperature, it is shown that a LOCOS done at a higher temperature will lead to sharper flating gate structure. Hence, we argue that it is better to perform LOCOS at high temperature as it leads to shorter oxidation time as well as sharper floating gate structure. |
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