OVERLAY PYNQ-ZL FOR COMPUTER ARCHITECTURE EDUCATION AND SIMULATION PROCESSOR WITH CACHE RISC-V EDITION

• Main Author: Salomo, Yahwista
• Format: Final Project
• Language: Indonesia
• Online Access: https://digilib.itb.ac.id/gdl/view/73294
• Institution: Institut Teknologi Bandung

The field of computer architecture is growing rapidly due to the emergence of an open source ISA standard called RISC-V [Waterman et al., 2014] which is the fifth genera­tion RISC(Reduced Instruction Set Computer) ISA developed at University of Califor­nia, Berkeley. There is an array of incentives that makes RISC-V a very promising ISA for electrical engineering students to study because its open source nature makes this standard easy for anyone to learn and modify. For example, a simulator, a SoC that can be imple­mented into a variety of commonly used FPGAs, cores wrapped in high-level HDL (Hardware Description Language) such as Migen [m labs, 2022], SpinalHDL [Spinal­HDL, 2022], Chisel3 [chi,], and etc. Other standards that have been used for computer architecture lessons include: MIPS, PIC, and AVR. Although most of the standards for studying architecture still use these standards, the benefits of studying the ISAs are getting smaller. Therefore, more and more universities every day are starting to use RISC-V as pivot entrance for students introduced to the RISC architecture. With the PYNQ framework which is intended primarily for students who want to inte­ract with the FPGA easily, the product created/modified is an overlay system (bitstream and tel description) which will be compressed into the FPGA and can be interacted di­rectly. There is also a RISC-V processor with a direct-mapped cache that has been ported to Vivado and can be simulated to interact to understand how the cache works on a processor.