NEORV32 OPEN SOURCE SOFT-CORE PROCESSOR IMPLEMENTATION ON FPGA

The use of processors in a system is very common. Processors often have licenses that require users to pay royalties to the license owner, for example the ARM-M0 which is widely used in industry. However, the license fee is also an entry barrier for academics and small industries to use licensed...

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Main Author: Arisaputra, Radithya
Format: Final Project
Language:Indonesia
Online Access:https://digilib.itb.ac.id/gdl/view/82232
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Institution: Institut Teknologi Bandung
Language: Indonesia
id id-itb.:82232
spelling id-itb.:822322024-07-06T13:53:13ZNEORV32 OPEN SOURCE SOFT-CORE PROCESSOR IMPLEMENTATION ON FPGA Arisaputra, Radithya Indonesia Final Project Processor, bus, UART, Wishbone, Open Source. INSTITUT TEKNOLOGI BANDUNG https://digilib.itb.ac.id/gdl/view/82232 The use of processors in a system is very common. Processors often have licenses that require users to pay royalties to the license owner, for example the ARM-M0 which is widely used in industry. However, the license fee is also an entry barrier for academics and small industries to use licensed processors. This research aims to implement an open source processor alternative to licensed processors that are common in the industry. NEORV32 based on RISC- V was chosen as a candidate to replace the licensed ARM-M0. Implementation was successfully done for internal bus, UART, and Wishbone components. Tests were conducted for the implemented components. Overall integration was also successful and system-level testing was conducted with the blink LED and Hello World programs written in C language, compiled, and simulated. Test results were obtained in the form of system behavior in accordance with algorithms written in C language. text
institution Institut Teknologi Bandung
building Institut Teknologi Bandung Library
continent Asia
country Indonesia
Indonesia
content_provider Institut Teknologi Bandung
collection Digital ITB
language Indonesia
description The use of processors in a system is very common. Processors often have licenses that require users to pay royalties to the license owner, for example the ARM-M0 which is widely used in industry. However, the license fee is also an entry barrier for academics and small industries to use licensed processors. This research aims to implement an open source processor alternative to licensed processors that are common in the industry. NEORV32 based on RISC- V was chosen as a candidate to replace the licensed ARM-M0. Implementation was successfully done for internal bus, UART, and Wishbone components. Tests were conducted for the implemented components. Overall integration was also successful and system-level testing was conducted with the blink LED and Hello World programs written in C language, compiled, and simulated. Test results were obtained in the form of system behavior in accordance with algorithms written in C language.
format Final Project
author Arisaputra, Radithya
spellingShingle Arisaputra, Radithya
NEORV32 OPEN SOURCE SOFT-CORE PROCESSOR IMPLEMENTATION ON FPGA
author_facet Arisaputra, Radithya
author_sort Arisaputra, Radithya
title NEORV32 OPEN SOURCE SOFT-CORE PROCESSOR IMPLEMENTATION ON FPGA
title_short NEORV32 OPEN SOURCE SOFT-CORE PROCESSOR IMPLEMENTATION ON FPGA
title_full NEORV32 OPEN SOURCE SOFT-CORE PROCESSOR IMPLEMENTATION ON FPGA
title_fullStr NEORV32 OPEN SOURCE SOFT-CORE PROCESSOR IMPLEMENTATION ON FPGA
title_full_unstemmed NEORV32 OPEN SOURCE SOFT-CORE PROCESSOR IMPLEMENTATION ON FPGA
title_sort neorv32 open source soft-core processor implementation on fpga
url https://digilib.itb.ac.id/gdl/view/82232
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