Development of process parameters for 22 nm PMOS using 2-D analytical modeling

The complementary metal-oxide-semiconductor field effect transistor (CMOSFET) has become major challenge to scaling and integration. Innovation in transistor structures and integration of novel materials are necessary to sustain this performance trend. CMOS variability in the scaling technology beco...

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Main Authors: Maheran A.H.A., Menon P.S., Ahmad I., Shaari S., Faizah Z.A.N.
Other Authors: 36570222300
Format: Conference Paper
Published: American Institute of Physics Inc. 2023
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spelling my.uniten.dspace-223602023-05-29T14:00:28Z Development of process parameters for 22 nm PMOS using 2-D analytical modeling Maheran A.H.A. Menon P.S. Ahmad I. Shaari S. Faizah Z.A.N. 36570222300 57201289731 12792216600 6603595092 56395444600 The complementary metal-oxide-semiconductor field effect transistor (CMOSFET) has become major challenge to scaling and integration. Innovation in transistor structures and integration of novel materials are necessary to sustain this performance trend. CMOS variability in the scaling technology becoming very important concern due to limitation of process control; over statistically variability related to the fundamental discreteness and materials. Minimizing the transistor variation through technology optimization and ensuring robust product functionality and performance is the major issue.In this article, the continuation study on process parameters variations is extended and delivered thoroughly in order to achieve a minimum leakage current (I LEAK ) on PMOS planar transistor at 22 nm gate length. Several device parameters are varies significantly using Taguchi method to predict the optimum combination of process parameters fabrication. A combination of high permittivity material (high-k) and metal gate are utilized accordingly as gate structure where the materials include titanium dioxide (TiO 2 ) and tungsten silicide (WSi x ). Then the L9 of the Taguchi Orthogonal array is used to analyze the device simulation where the results of signal-to-noise ratio (SNR) of Smaller-the-Better (STB) scheme are studied through the percentage influences of the process parameters. This is to achieve a minimum I LEAK where the maximum predicted I LEAK value by International Technology Roadmap for Semiconductors (ITRS) 2011 is said to should not above 100 nA/?m. Final results shows that the compensation implantation dose acts as the dominant factor with 68.49% contribution in lowering the device's leakage current. The absolute process parameters combination results in I LEAK mean value of 3.96821 nA/?m where is far lower than the predicted value. � 2015 AIP Publishing LLC. Final 2023-05-29T06:00:28Z 2023-05-29T06:00:28Z 2015 Conference Paper 10.1063/1.4915157 2-s2.0-84988304504 https://www.scopus.com/inward/record.uri?eid=2-s2.0-84988304504&doi=10.1063%2f1.4915157&partnerID=40&md5=6c4ed198e97335efe62341b7d946451d https://irepository.uniten.edu.my/handle/123456789/22360 1657 30007 American Institute of Physics Inc. Scopus
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description The complementary metal-oxide-semiconductor field effect transistor (CMOSFET) has become major challenge to scaling and integration. Innovation in transistor structures and integration of novel materials are necessary to sustain this performance trend. CMOS variability in the scaling technology becoming very important concern due to limitation of process control; over statistically variability related to the fundamental discreteness and materials. Minimizing the transistor variation through technology optimization and ensuring robust product functionality and performance is the major issue.In this article, the continuation study on process parameters variations is extended and delivered thoroughly in order to achieve a minimum leakage current (I LEAK ) on PMOS planar transistor at 22 nm gate length. Several device parameters are varies significantly using Taguchi method to predict the optimum combination of process parameters fabrication. A combination of high permittivity material (high-k) and metal gate are utilized accordingly as gate structure where the materials include titanium dioxide (TiO 2 ) and tungsten silicide (WSi x ). Then the L9 of the Taguchi Orthogonal array is used to analyze the device simulation where the results of signal-to-noise ratio (SNR) of Smaller-the-Better (STB) scheme are studied through the percentage influences of the process parameters. This is to achieve a minimum I LEAK where the maximum predicted I LEAK value by International Technology Roadmap for Semiconductors (ITRS) 2011 is said to should not above 100 nA/?m. Final results shows that the compensation implantation dose acts as the dominant factor with 68.49% contribution in lowering the device's leakage current. The absolute process parameters combination results in I LEAK mean value of 3.96821 nA/?m where is far lower than the predicted value. � 2015 AIP Publishing LLC.
author2 36570222300
author_facet 36570222300
Maheran A.H.A.
Menon P.S.
Ahmad I.
Shaari S.
Faizah Z.A.N.
format Conference Paper
author Maheran A.H.A.
Menon P.S.
Ahmad I.
Shaari S.
Faizah Z.A.N.
spellingShingle Maheran A.H.A.
Menon P.S.
Ahmad I.
Shaari S.
Faizah Z.A.N.
Development of process parameters for 22 nm PMOS using 2-D analytical modeling
author_sort Maheran A.H.A.
title Development of process parameters for 22 nm PMOS using 2-D analytical modeling
title_short Development of process parameters for 22 nm PMOS using 2-D analytical modeling
title_full Development of process parameters for 22 nm PMOS using 2-D analytical modeling
title_fullStr Development of process parameters for 22 nm PMOS using 2-D analytical modeling
title_full_unstemmed Development of process parameters for 22 nm PMOS using 2-D analytical modeling
title_sort development of process parameters for 22 nm pmos using 2-d analytical modeling
publisher American Institute of Physics Inc.
publishDate 2023
_version_ 1806424286829740032