Characterization of fabrication process noises for 32nm NMOS devices

• Main Authors: Elgomati H.A., Majlis B.Y., Ahmad I., Ziad T.
• Other Authors: 36536722700
• Format: Conference Paper
• Published: 2023
• Subjects: Fabrication; MOS devices; Semiconductor growth; Silicides; Taguchi methods; Threshold voltage; Annealing temperatures; Degree of noise; Diffusion temperature; Fabrication process; Nanometer device; NMOS devices; NMOS transistors; Optimum fabrication; Sacrificial oxide; Transistors
• Institution: Universiti Tenaga Nasional

This paper describes the effect of fabrication process noises to Sub-nanometer devices, which in this case a 32nm NMOS transistor. This experiment a part of a full Taguchi Method analysis to obtain an optimum fabrication recipe for the said transistor. The two noises introduced in the fabrication is �1�C variation in sacrificial oxide layer growth by diffusion temperature and also silicide compress annealing temperature. In this project, a working 32 NMOS transistor fabrication is used. By increasing the sacrificial oxide layer diffusion temperature from 900�C to 901�C, the reference 32nm NMOS transistor threshold voltage (VTH) jumps from 0.1181V to 0.1394V, while leakage current drops from 0.111mA/um to 0.109 mA/um. By decreasing the silicide compress temperature from 910�C to 909�C, threshold voltage increase slightly from 0.118053V to 0.118068V, This shows a very different in magnitude of effect from same degree of noise introduce to the fabrication process. � 2010 IEEE.