Scaling down of the 32 nm to 22 nm gate length NMOS transistor

In this paper, we provide the downscaling design and simulation of NMOS transistor with 22 nm gate length, based on the 32 nm design simulation from our previous research. A combination Titanium dioxide (TiO2) was used as the high-k material and tungsten silicide (WSix) was used as the metal gate in...

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Main Authors:	Afifah Maheran, A.H., Menon, P.S., Ahmad, I., Elgomati, H.A., Majlis, B.Y., Salehuddin, F.
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Published:	2017
Online Access:	http://dspace.uniten.edu.my:8080/jspui/handle/123456789/5224
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Institution:	Universiti Tenaga Nasional

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spelling	my.uniten.dspace-52242017-11-15T02:56:46Z Scaling down of the 32 nm to 22 nm gate length NMOS transistor Afifah Maheran, A.H. Menon, P.S. Ahmad, I. Elgomati, H.A. Majlis, B.Y. Salehuddin, F. In this paper, we provide the downscaling design and simulation of NMOS transistor with 22 nm gate length, based on the 32 nm design simulation from our previous research. A combination Titanium dioxide (TiO2) was used as the high-k material and tungsten silicide (WSix) was used as the metal gate instead of SiO2 dielectric from the 32 nm gate length device. The NMOS transistor was simulated using fabrication tool ATHENA and electrical characterization was simulated using ATLAS. The scale down ratio was used and the dimension of device was scaled down with minimal issues. Our simulation shows that the optimal value of threshold voltage (Vth) and leakage currents (Ion and Ioff) was achieved according to specification in ITRS 2011. This provides a benchmark towards the fabrication of 22 nm NMOS in future work. © 2012 IEEE. 2017-11-15T02:56:46Z 2017-11-15T02:56:46Z 2012 http://dspace.uniten.edu.my:8080/jspui/handle/123456789/5224
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continent	Asia
country	Malaysia
content_provider	Universiti Tenaga Nasional
content_source	UNITEN Institutional Repository
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description	In this paper, we provide the downscaling design and simulation of NMOS transistor with 22 nm gate length, based on the 32 nm design simulation from our previous research. A combination Titanium dioxide (TiO2) was used as the high-k material and tungsten silicide (WSix) was used as the metal gate instead of SiO2 dielectric from the 32 nm gate length device. The NMOS transistor was simulated using fabrication tool ATHENA and electrical characterization was simulated using ATLAS. The scale down ratio was used and the dimension of device was scaled down with minimal issues. Our simulation shows that the optimal value of threshold voltage (Vth) and leakage currents (Ion and Ioff) was achieved according to specification in ITRS 2011. This provides a benchmark towards the fabrication of 22 nm NMOS in future work. © 2012 IEEE.
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author	Afifah Maheran, A.H. Menon, P.S. Ahmad, I. Elgomati, H.A. Majlis, B.Y. Salehuddin, F.
spellingShingle	Afifah Maheran, A.H. Menon, P.S. Ahmad, I. Elgomati, H.A. Majlis, B.Y. Salehuddin, F. Scaling down of the 32 nm to 22 nm gate length NMOS transistor
author_facet	Afifah Maheran, A.H. Menon, P.S. Ahmad, I. Elgomati, H.A. Majlis, B.Y. Salehuddin, F.
author_sort	Afifah Maheran, A.H.
title	Scaling down of the 32 nm to 22 nm gate length NMOS transistor
title_short	Scaling down of the 32 nm to 22 nm gate length NMOS transistor
title_full	Scaling down of the 32 nm to 22 nm gate length NMOS transistor
title_fullStr	Scaling down of the 32 nm to 22 nm gate length NMOS transistor
title_full_unstemmed	Scaling down of the 32 nm to 22 nm gate length NMOS transistor
title_sort	scaling down of the 32 nm to 22 nm gate length nmos transistor
publishDate	2017
url	http://dspace.uniten.edu.my:8080/jspui/handle/123456789/5224
_version_	1644493620514914304

Scaling down of the 32 nm to 22 nm gate length NMOS transistor

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