An efficient first order sigma delta modulator design
An efficient first order sigma delta modulator has been designed in circuit level, considering the possible non-idealities in 65 nm CMOS technology. This study at first determines the non-idealities of sigma delta modulator. The non-idealities investigated here are clock jitter noise that effects th...
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| Main Authors: | , , |
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| Format: | |
| Published: |
2017
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| Online Access: | http://dspace.uniten.edu.my:8080/jspui/handle/123456789/5282 |
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| Institution: | Universiti Tenaga Nasional |