An efficient first order sigma delta modulator design
An efficient first order sigma delta modulator has been designed in circuit level, considering the possible non-idealities in 65 nm CMOS technology. This study at first determines the non-idealities of sigma delta modulator. The non-idealities investigated here are clock jitter noise that effects th...
Saved in:
| Main Authors: | , , |
|---|---|
| Format: | |
| Published: |
2017
|
| Online Access: | http://dspace.uniten.edu.my:8080/jspui/handle/123456789/5282 |
| Tags: |
Add Tag
No Tags, Be the first to tag this record!
|
| Institution: | Universiti Tenaga Nasional |
Be the first to leave a comment!